AK4371 Datasheet, PDF (48/62 Pages) Asahi Kasei Microsystems – DAC with built-in PLL & HP-AMP

[AK4371]
■ Register Map
Addr
00H
01H
02H
03H
04H
05H
06H
07H
08H
09H
0AH
0BH
0CH
0DH
0EH
0FH
10H
11H
12H
13H
Register Name
Power Management 0
PLL Control
Clock Control
Mode Control 0
Mode Control 1
DAC Lch ATT
DAC Rch ATT
Headphone Out Select 0
Lineout Select 0
Lineout ATT
Reserved
Reserved
Reserved
Headphone Out Select
Headphone ATT
Lineout Select
Mono Mixing
Differential Select
MOUT Select
MOUT ATT
D7
PMVREF
FS3
PLL4
0
ATS
ATTL7
ATTR7
HPG1
0
0
0
0
0
RIN3HR
0
RIN3R
0
0
RIN3M
0
D6
PMPLL
FS2
0
MONO1
DATTC
ATTL6
ATTR6
HPG0
LOG
0
0
0
0
RIN3HL
HPZ
RIN3L
0
0
LIN3M
PMMO
D5
PMLO
FS1
M/S
MONO0
LMUTE
ATTL5
ATTR5
LIN2HR
LIN2R
0
0
0
0
LIN3HR
HMUTE
LIN3R
L3M
0
RIN2M
MOG
D4
MUTEN
FS0
MCKAC
BCKP
SMUTE
ATTL4
ATTR4
LIN2HL
LIN2L
0
0
0
0
LIN3HL
ATTH4
LIN3L
L3HM
0
LIN2M
MMUTE
D3
PMHPR
PLL3
BF
LRP
BST1
ATTL3
ATTR3
RIN1HR
RIN1R
ATTS3
0
0
0
RIN2HR
ATTH3
RIN2R
L2M
0
RIN1M
ATTM3
D2
PMHPL
PLL2
PS0
DIF2
BST0
ATTL2
ATTR2
LIN1HL
LIN1L
ATTS2
0
0
0
RIN2HL
ATTH2
RIN2L
L2HM
LDIFM
LIN1M
ATTM2
D1
PMDAC
PLL1
PS1
DIF1
DEM1
ATTL1
ATTR1
DARHR
DARR
ATTS1
0
0
0
LIN1HR
ATTH1
LIN1R
L1M
LDIFH
DARM
ATTM1
D0
PMVCM
PLL0
MCKO
DIF0
DEM0
ATTL0
ATTR0
DALHL
DALL
ATTS0
0
0
0
RIN1HL
ATTH0
RIN1L
L1HM
LDIF
DALM
ATTM0
All registers inhibit writing at PDN pin = “L”.
PDN pin = “L” resets the registers to their default values.
For addresses from 14H to 1FH, data must not be written.
Unused bits must contain a “0” value.
MS0596-E-00
- 48 -
2007/04