AK4371 Datasheet, PDF (14/62 Pages) Asahi Kasei Microsystems – DAC with built-in PLL & HP-AMP

Parameter
Symbol
min
typ
Control Interface Timing (I²C Bus mode): (Note 29)
SCL Clock Frequency
fSCL
-
-
Bus Free Time Between Transmissions
tBUF
1.3
-
Start Condition Hold Time (prior to first clock pulse) tHD:STA
0.6
-
Clock Low Time
tLOW
1.3
-
Clock High Time
tHIGH
0.6
-
Setup Time for Repeated Start Condition
tSU:STA
0.6
-
SDA Hold Time from SCL Falling (Note 30)
tHD:DAT
0
-
SDA Setup Time from SCL Rising
tSU:DAT
0.1
-
Rise Time of Both SDA and SCL Lines
tR
-
-
Fall Time of Both SDA and SCL Lines
tF
-
-
Setup Time for Stop Condition
tSU:STO
0.6
-
Capacitive Load on Bus
Cb
-
-
Pulse Width of Spike Noise Suppressed by Input Filter tSP
0
-
Power-down & Reset Timing
PDN Pulse Width (Note 31)
tPD
150
-
Note 29. I²C is a registered trademark of Philips Semiconductors.
Note 30. Data must be held long enough to bridge the 300ns-transition time of SCL.
Note 31. The AK4371 can be reset by bringing PDN pin = “L” to “H” only upon power up.
[AK4371]
max
Units
400
kHz
-
μs
-
μs
-
μs
-
μs
-
μs
-
μs
-
μs
0.3
μs
0.3
μs
-
μs
400
pF
50
ns
-
ns
MS0596-E-00
- 14 -
2007/04