AK4371 Datasheet, PDF (50/62 Pages) Asahi Kasei Microsystems – DAC with built-in PLL & HP-AMP

[AK4371]
Addr
01H
Register Name
PLL Control
R/W
Default
D7
D6
D5
D4
D3
D2
D1
D0
FS3
FS2
FS1
FS0 PLL3 PLL2 PLL1 PLL0
R/W R/W R/W R/W R/W R/W R/W R/W
1
0
0
0
0
0
0
0
FS3-0: Select Sampling Frequency
PLL mode: Table 5
EXT mode: Table 11
PLL4-0: Select PLL Reference Clock
PLL mode: Table 4
EXT mode: PLL4-0 bits are disabled
(PLL4 bit is D7 bit of 02H.)
Addr
02H
Register Name
Clock Control
R/W
Default
D7
D6
PLL4
0
R/W RD
0
0
D5
D4
D3
D2
D1
D0
M/S MCKAC BF
PS0
PS1 MCKO
R/W R/W R/W R/W R/W R/W
0
0
0
0
0
0
MCKO: Control of MCKO signal
0: Disable (default)
1: Enable
PS1-0: MCKO Frequency
PLL mode: Table 9
EXT mode: Table 12
BF: BICK Period setting in Master Mode. In slave mode, this bit is ignored.
0: 32fs (default)
1: 64fs
MCKAC: MCKI Input Mode Select
0: CMOS input (default)
1: AC coupling input
M/S: Select Master/Slave Mode
0: Slave mode (default)
1: Master mode
PLL4-0: Select PLL Reference Clock
PLL3-0 bits are D3-0 bits of 01H.
MS0596-E-00
- 50 -
2007/04