LU3X54FTL Datasheet, PDF (5/52 Pages) Agere Systems – QUAD-FET for 10Base-T/100Base-TX/FX

Data Sheet
July 2000
LU3X54FTL
QUAD-FET for 10Base-T/100Base-TX/FX
Description (continued)
The bused mode has two additional submodes of
operation:
s Separate Bused MII Mode. This mode is designed
to operate with two independent repeater ICs, one
repeater operating at 100 Mbits/s and the other oper-
ating at 10 Mbits/s.
Figure 6 shows a block diagram of this mode in
which separate pins (four of each) are used for
COL_10(4), COL_100(4), CRS_10(4), CRS_100(4),
RX_EN10(4), RX_EN100(4), TX_EN10 (4), and
TX_EN100(4).
The signals RX_CLK10, RXD_10, TX_CLK10, and
TXD_10 (all from ports A, B, C, and D) are internally
bused together and connected to MII port B.
The signals TX_CLK25, TXD_100[3:0], TX_ER,
RX_CLK25, RXD_100[3:0], RX_DV, and RX_ER (all
from ports A, B, C, D) are internally bused together
and connected to MII port A.
The repeater ICs will enable the particular port to
which it will communicate by enabling the port with
TX_EN 10, TX_EN100, RX_EN10, or RX_EN100.
s Smart Bused MII Mode. This mode is used when
the LU3X54FTL is communicating with a single
(smart) 10/100 Mbits/s repeater IC, and allows the
use of the security feature.
Figure 5 shows a block diagram of the smart bused
mode of operation. In this mode, a common set of
pins is used for CRS_10/100[D:A],
RX_EN10/100[D:A], TX_EN10/100, and
COL_10/100.
The 10 Mbits/s (7-pin 10 Mbits/s serial interface) sig-
nals are still routed to port B (RX_CLK10, RXD_10,
TX_CLK10, and TXD_10).
The 100 Mbits/s signals are still routed to port A
(TX_CLK25, TXD_100[3:0], TX_ER, RX_CLK25,
RXD_100[3:0], RX_DV, and RX_ER).
The bused interface allows each of the four transceiv-
ers to be connected to one of two system interfaces:
s Port A: 100 Mbits/s MII interface.
s Port B: 7-pin 10 Mbits/s serial interface.
This configuration allows 10/100 Mbits/s segment seg-
regation or port switching with conventional multiport
shared-media repeaters.
The port speed configuration and connection to the
appropriate bused output is done automatically and is
controlled by autonegotiation.
Figure 1 gives a functional overview of the LU3X54FTL
while Figure 2 details its single-channel functions.
Figure 3 shows how the LU3X54FTL single-channel
interfaces to the twisted pair (TP).
Clocking
The LU3X54FTL requires an internal 25 MHz clock and
a 20 MHz clock to run the 100Base-TX transceiver and
10Base-T transceiver.
These clocks can be supplied as follows:
s As separate clock inputs: 25 MHz and 20 MHz.
s The 20 MHz clock can be internally synthesized from
the 25 MHz clock.
s The 25 MHz clock can also be internally generated
by an on-chip oscillator if an external crystal is sup-
plied.
The LU3X54FTL will automatically detect if a 25 MHz
clock is supplied, or if a crystal is being used to gener-
ate the 25 MHz clock.
Lucent Technologies Inc.
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