LU3X54FTL Datasheet, PDF (38/52 Pages) Agere Systems – QUAD-FET for 10Base-T/100Base-TX/FX

LU3X54FTL
QUAD-FET for 10Base-T/100Base-TX/FX
Data Sheet
July 2000
MII Station Management (continued)
Table 21. MR30—Device-Specific Register 3 (10 Mbits/s Control) Bit Descriptions
Register/Bit¹
30.15:7 (R28[15:7])
30.6 (CLK_SEL)
30.5 (HBT_EN)
30.4 (ELL_EN)
30.3 (APF_DIS)
Type²
R/W
R/W
R/W
R/W
R/W
Description
Unused. Read as 0.
20 MHz Clock Select. When this bit is a 1, it enables the two-clock input mode
(20 MHz and 25 MHz). When this bit is a 0, it enables the single-clock input
mode 25 MHz (with 20 MHz clock internally generated). Default state is 0.
Heartbeat Enable. When this bit is a 1, the heartbeat function will be
enabled. Valid in 10 Mbits/s mode only. Default state is 0.
Extended Line Length Enable. When this bit is a 1, the receive squelch
levels are reduced from a nominal 435 mV to 350 mV, allowing reception of
signals with a lower amplitude. Valid in 10 Mbits/s mode only. Default state is
0.
Autopolarity Function Disable. When this bit is a 0 and the LU3X54FTL is in
10 Mbits/s mode, the autopolarity function will determine if the TP link is wired
with a polarity reversal.
30.2 (REF_SEL)
30.1 (SERIAL _SEL)
30.0 (ENA_NO_LP)
If there is a polarity reversal, the LU3X54FTL will assert the APS bit (register
28, bit 6) and correct the polarity reversal. If this bit is a 1 and the device is in
10 Mbits/s mode, the reversal will not be corrected. Default state is 0.
R/W Reference Select. When this bit is a 1, the external 10 MHz reference input
clock REF10 is used for phase alignment. Default state is 0.
R/W Serial Select. When this bit is set to a 1, 10 Mbits/s serial mode will be
selected. When the LU3X54FTL is in 100 Mbits/s mode, this bit will be
ignored. This bit is ORed with the H_DUPLED[C] pin during powerup and
reset. Default state is 0.
R/W No Link Pulse Mode. Setting this bit to a 1 will allow 10 Mbits/s operation
with link pulses disabled. If the LU3X54FTL is configured for 100 Mbits/s oper-
ation, setting this bit will not affect operation. This bit is ORed with the
LINKLED[A] pin during powerup and reset. Default state is 0.
1. Note that the format for the bit descriptions is as follows: the first number is the register number, the second number is the bit position in the
register, and the name of the instantiated pad is in capital letters.
2 R = read, W = write.
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