LU3X54FTL Datasheet, PDF (25/52 Pages) Agere Systems – QUAD-FET for 10Base-T/100Base-TX/FX

Data Sheet
July 2000
LU3X54FTL
QUAD-FET for 10Base-T/100Base-TX/FX
Pin Information (continued)
Table 7. Miscellaneous Pins (continued)
Pin
171—168
176—173
190
189
188
187
Signal
RXLED[D:A]/
FX_MODE_EN[D:A]
COLED[D:A]
LINKLED[D]/
PHYADD[2]
LINKLED[C]/
PHYADD[1]
LINKLED[B]/
PHYADD[0]
LINKLED[A]/
NO_LP
Type
Description
I/O Receive LED[D:A]. This pin indicates receive activity. External buffers
are necessary to drive the LEDs.
FX Mode Enable. At powerup or reset, when pulled high through a
4.7 kΩ resistor, this pin will enable the FX mode (10Base-T and
100Base-TX disabled). When pulled low, it will enable 10Base-T and
100Base_TX modes (100Base-FX mode disabled). These pins are
ORed with register 29, bit 0 [29.0].
These pins have internal 50 kΩ pull-down resistors.
O Collision LED. This pin indicates collision occurrence. External buffers
are necessary to drive the LEDs.
Channels A and B have internal 50 kΩ pull-down resistors but not
channels C and D.
I/O Link LED[D]. This pin indicates good link status on port D. External
buffers are necessary to drive the LEDs.
PHY Address 2. At powerup or reset, this pin is used to set the PHY
address bit 2.
If this pin is pulled high through a 50 kΩ resistor, it will set PHYADD[2]
to a 1. If this pin is pulled low through a 50 kΩ resistor, it will set
PHYADD[2] to a 0.
I/O Link LED[C]. This pin indicates good link status on port C. External
buffers are necessary to drive the LEDs.
PHY Address 1. At powerup or reset, this pin is used to set the PHY
address bit 1.
If this pin is pulled high through a 50 kΩ resistor, it will set PHYADD[1]
to a 1. If this pin is pulled low through a 50 kΩ resistor, it will set
PHYADD[1] to a 0.
I/O Link LED[B]. This pin indicates good link status on port B. External
buffers are necessary to drive the LEDs.
PHY Address 0. At powerup or reset, this pin may be used to set the
PHY address bit 0.
If this pin is pulled high through a 50 kΩ resistor, it will set PHYADD[0]
to a 1. If this pin is pulled low through a 50 kΩ resistor, it will set
PHYADD[0] to a 0.
I/O Link LED[A]. This pin indicates good link status on port A. External
buffers are necessary to drive the LEDs.
No Link Pulse. This pin is used at powerup or reset to select the
NO_LP function of register 30, bit 0 for all four channels by pulling this
pin high through a 4.7 kΩ resistor. This input and the register bit [30.0]
are ORed together.
This pin has an internal 50 kΩ pull-down resistor to set the default to
normal link pulse ON mode.
Lucent Technologies Inc.
25