LU3X54FTL Datasheet, PDF (3/52 Pages) Agere Systems – QUAD-FET for 10Base-T/100Base-TX/FX

Data Sheet
July 2000
LU3X54FTL
QUAD-FET for 10Base-T/100Base-TX/FX
Table of Contents ^(continued)
Tables
Page
Table 17. MR6—Autonegotiation Expansion Register Bit Descriptions..................................................................35
Table 18. MR7—Next-Page Transmit Register Bit Descriptions .............................................................................35
Table 19. MR28—Device-Specific Register 1 (Status Register) Bit Descriptions...................................................36
Table 20. MR29—Device-Specific Register 2 (100 Mbits/s Control) Bit Descriptions ............................................37
Table 21. MR30—Device-Specific Register 3 (10 Mbits/s Control) Bit Descriptions ..............................................38
Table 22. MR31—Device-Specific Register 4 (Quick Status) Bit Descriptions.......................................................39
Table 23. Output Pins .............................................................................................................................................40
Table 24. LU3X54FTL Modes.................................................................................................................................40
Table 25. Absolute Maximum Ratings ....................................................................................................................41
Table 26. Operating Conditions ..............................................................................................................................41
Table 27. dc Characteristics ...................................................................................................................................41
Table 28. MII Management Interface Timing (25 pF Load).....................................................................................42
Table 29. MII Data Timing (25 pF Load) .................................................................................................................43
Table 30. Serial 10 Mbits/s Timing for TPIN, CRS, and RX_CLK...........................................................................45
Table 31. Serial 10 Mbits/s Timing for TX_EN, TPOUT, CRS, and RX_CLK..........................................................45
Table 32. Serial 10 Mbits/s Timing for TX_EN, TPIN, and COL .............................................................................46
Table 33. Serial 10 Mbits/s Timing for RX_CLK, CRS, RXD, TX_CLK, TX_EN, and TXD (25 pF Load)................47
Table 34. Serial 10 Mbits/s Timing for RX_CLK and TX_CLK (25 pF Load) ..........................................................48
Table 35. 100 Mbits/s MII Transmit Timing .............................................................................................................49
Table 36. 100 Mbits/s MII Receive Timing..............................................................................................................50
Figures
Page
Figure 1. LU3X54FTL Device Overview...................................................................................................................7
Figure 2. LU3X54FTL Single-Channel Detail Functions ..........................................................................................8
Figure 3. Typical Single-Channel Twisted-Pair (TP) Interface ..................................................................................9
Figure 4. Typical Single-Channel Fiber-Optic Interface ..........................................................................................10
Figure 5. Smart 10/100 Mbits/s Bused MII Mode...................................................................................................11
Figure 6. Separate 10/100 Mbits/s Bused MII Mode ..............................................................................................12
Figure 7. LU3X54FTL Pinout for Normal MII Mode................................................................................................13
Figure 8. LU3X54FTL Pinout for Bused MII Mode .................................................................................................14
Figure 9. MDIO Input Timing..................................................................................................................................42
Figure 10. MDIO Output Timing .............................................................................................................................42
Figure 11. MDIO During TA (Turnaround) of a Read Transaction ..........................................................................43
Figure 12. MII Timing Requirements for LU3X54FTL ............................................................................................44
Figure 13. Serial 10 Mbits/s Timing for TPIN, CRS, and RX_CLK.........................................................................45
Figure 14. Serial 10 Mbits/s Timing for TX_EN, TPOUT, CRS, and RX_CLK........................................................45
Figure 15. Serial 10 Mbits/s Timing for TX_EN, TPIN, and COL ...........................................................................46
Figure 16. Serial 10 Mbits/s Timing for RX_CLK, CRS, RXD, TX_CLK, TX_EN, and TXD ...................................47
Figure 17. Serial 10 Mbits/s Timing Diagram for RX_CLK and TX_CLK ...............................................................48
Figure 18. 100 Mbits/s MII Transmit Timing ...........................................................................................................49
Figure 19. 100 Mbits/s MII Receive Timing ............................................................................................................50
Lucent Technologies Inc.
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