LU3X54FTL Datasheet, PDF (31/52 Pages) Agere Systems – QUAD-FET for 10Base-T/100Base-TX/FX

Data Sheet
July 2000
LU3X54FTL
QUAD-FET for 10Base-T/100Base-TX/FX
MII Station Management (continued)
This section provides a detailed discussion of each management register and its bit definitions.
Table 11. MR0—Control Register Bit Descriptions
Register/Bit¹
0.15 (SW_RESET)
0.14 (LOOPBACK)
0.13 (SPEED100)
0.12 (NWAY_ENA)
0.11 (PWRDN)
0.10 (ISOLATE)
0.9 (REDONWAY)
0.8 (FULL_DUP)
0.7 (COLTST)
0.6:0 (RESERVED)
Type²
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
NA
Description
Reset. Setting this bit to a 1 will reset the entire (all 4 ports, even when only 1
port is addressed) LU3X54FTL. All registers will be set to their default state.
This bit is self-clearing. The default is 0.
Loopback. When this bit is set to 1, no data transmission will take place on
the media. Any receive data will be ignored. The loopback signal path will con-
tain all circuitry up to but not including the PMD. The default value is a 0.
Speed Selection. The value of this bit reflects the current speed of operation
(1 = 100 Mbits/s, 0 = 10 Mbits/s). This bit will only affect operating speed when
the autonegotiation enable bit (register 0, bit 12) is disabled (0). This bit is
ignored when autonegotiation is enabled (register 0, bit 12). This bit is ANDed
with the SPEEDLED[D] pin during powerup and reset. The default state is a 1.
Autonegotiation Enable. The autonegotiation process will be enabled by set-
ting this bit to a 1. The default state is a 1.
Powerdown. The LU3X54FTL may be placed in a low-power state by setting
this bit to a 1, both the 10 Mbits/s transceiver and the 100 Mbits/s transceiver
will be powered down. While in the powerdown state, the LU3X54FTL will
respond to management transactions. The default state is a 0.
Isolate Mode. When this bit is set to a 1, the MII outputs will be brought to the
high-impedance state. The default state is a 0. This bit is ORed with the
SPEEDLED[A]/ISOLATE_MODE pin during powerup and reset.
Restart Autonegotiation. Normally, the autonegotiation process is started at
powerup. The process may be restarted by setting this bit to a 1. The default
state is a 0. The NWAYDONE bit (register 1, bit 5) is reset when this bit goes
to a 1. This bit is self-cleared when autonegotiation restarts.
Duplex Mode. This bit reflects the mode of operation (1 = full duplex, 0 = half
duplex). This bit is ignored when the autonegotiation enable bit (register 0,
bit 12) is enabled. The default state is a 0. This bit is ORed with the
H_DUPLED[D] pin during powerup or reset.
Collision Test. When this bit is set to a 1, the LU3X54FTL will assert the COL
signal in response to TX_EN. This bit should only be set when in loopback
mode.
Reserved. All bits will read 0.
1. Note that the format for the bit descriptions is as follows: the first number is the register number, the second number is the bit position in the
register, and the name of the instantiated pad is in capital letters.
2. R = read, W = write, NA = not applicable.
Lucent Technologies Inc.
31