LU3X54FTL Datasheet, PDF (36/52 Pages) Agere Systems – QUAD-FET for 10Base-T/100Base-TX/FX

LU3X54FTL
QUAD-FET for 10Base-T/100Base-TX/FX
Data Sheet
July 2000
MII Station Management (continued)
Table 19. MR28—Device-Specific Register 1 (Status Register) Bit Descriptions
Register/Bit¹
28.15:9 (R28[15:9])
28.8 (BAD_FRM)
Type²
R
R/LH
Description
Unused. Read as 0.
Bad Frame. If this bit is a 1, it indicates a packet has been received without an
SFD. This bit is only valid in 10 Mbits/s mode.
28.7 (CODE)
R/LH
This bit is latching high and will only clear after it has been read or the device
has been reset. This bit defaults to 0.
Code Violation. When this bit is a 1, it indicates a Manchester code violation
has occurred. The error code will be output on the RXD lines. Refer to Table 3
for a detailed description of the RXD pin error codes. This bit is only valid in
10 Mbits/s mode.
28.6 (APS)
This bit is latching high and will only clear after it has been read or the device
has been reset. This bit defaults to 0.
R Autopolarity Status. When register 30, bit 3 is set and this bit is a 1, it indi-
cates the LU3X54FTL has detected and corrected a polarity reversal on the
twisted pair.
28.5 (DISCON)
28.4 (UNLOCKED)
28.3 (RXERR_ST)
28.2 (FRC_JAM)
28.1 (LNK100UP)
28.0 (LNK10UP)
R/LH
R/LH
R/LH
R/LH
R
R
If the APF_EN bit (register 30, bit 3) is set, the reversal will be corrected inside
the LU3X54FTL. This bit is not valid in 100 Mbits/s operation. This bit defaults
to 0.
Disconnect. If this bit is a 1, it indicates a disconnect. This bit will latch high
until read. This bit is only valid in 100 Mbits/s mode. This bit defaults to 0.
Unlocked. Indicates that the TX scrambler lost lock. This bit will latch high until
read. This bit is only valid in 100 Mbits/s mode. This bit defaults to 0.
RX Error Status. Indicates a false carrier. This bit will latch high until read. This
bit is only valid in 100 Mbits/s mode. This bit defaults to 0.
Force Jam. This bit will latch high until read. This bit is only valid in 100 Mbits/s
mode. This bit defaults to 0.
Link Up 100. This bit, when set to a 1, indicates a 100 Mbits/s transceiver is up
and operational. This bit defaults to 0.
Link Up 10. This bit, when set to a 1, indicates a 10 Mbits/s transceiver is up
and operational. This bit defaults to 0.
1. Note that the format for the bit descriptions is as follows: the first number is the register number, the second number is the bit position in the
register, and the name of the instantiated pad is in capital letters.
2. R = read, LH = latched high.
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