LU3X54FTL Datasheet, PDF (16/52 Pages) Agere Systems – QUAD-FET for 10Base-T/100Base-TX/FX

LU3X54FTL
QUAD-FET for 10Base-T/100Base-TX/FX
Data Sheet
July 2000
Pin Information (continued)
Pin Descriptions
This section describes the LU3X54FTL signal pins. Note that any register bit referenced includes the register num-
ber and bit position. For example, register bit [29.8] is register 29, bit 8.
Table 3. MII/Serial Interface Pins in Normal MII Mode (Four Separate MII Ports)
Pin
Signal
Type
Description
100
COL[D:A]
O Collision Detect. This signal signifies in half-duplex mode that a collision
67
has occurred on the network. COL is asserted high whenever there is
150
transmit and receive activity on the UTP media. COL is the logical AND of
127
TX_EN and receive activity, and is an asynchronous output. When
SERIAL_SEL is high and in 10Base-T mode, this signal indicates the jab-
ber timer has expired.
99
CRS[D:A]
O Carrier Sense. When CRS_SEL is low, this signal is asserted high when
66
either the transmit or receive medium is nonidle. This signal remains
149
asserted throughout a collision condition. When CRS_SEL is high, CRS is
126
asserted on receive activity only. CRS_SEL is set via the MII management
interface or the CRS_SEL pin.
104
RX_CLK[D:A] O Receive Clock. 25 MHz clock output in 100 Mbits/s mode, 2.5 MHz output
71
in 10 Mbits/s nibble mode, 10 MHz in 10 Mbits/s serial mode. RX_CLK has
154
a worst-case 45/55 duty cycle. RX_CLK provides the timing reference for
131
the transfer of RX_DV, RXD, and RX_ER signals.
109
RXD[3:0][D:A] O Receive Data. 4-bit parallel data outputs that are synchronous to RX_CLK.
76
When RX_ER[D:A] is asserted high in 100 Mbits/s mode, an error code will
159
be presented on RXD[3:0][D:A] where appropriate. The codes are as fol-
136
lows:
108
s Packet errors: ERROR_CODES = 2h.
75
158
s Link errors: ERROR_CODES = 3h. (Packet and link error codes will only
135
be repeated if registers [29.9] and [29.8] are enabled.)
107
s Premature end errors: ERROR_CODES = 4h.
74
157
s Code errors: ERROR_CODES = 5h.
134
When SERIAL_SEL is active-high and 10 Mbits/s mode is selected, RXD[0]
105
is used for data output and RXD[3:1] are 3-stated.
72
155
132
101
RX_DV[D:A] O Receive Data Valid. When this pin is high, it indicates the LU3X54FTL is
68
recovering and decoding valid nibbles on RXD[3:0], and the data is syn-
151
chronous with RX_CLK. RX_DV is synchronous with RX_CLK. This pin is
128
not used in serial 10 Mbits/s mode.
103
RX_ER[D:A]/ O Receive Error. When high, RX_ER indicates the LU3X54FTL has detected
70
RXD[4][D:A]
a coding error in the frame presently being transferred. RX_ER is synchro-
153
nous with RX_CLK.
130
Receive Data[4]. When encoder/decoder bypass (ENC_DEC_BYPASS) is
selected through the MII management interface, this output serves as the
RXD[4] output. This pin is only valid when the LU3X54FTL is in 100 Mbits/s
mode.
16
Lucent Technologies Inc.