LU3X54FTL Datasheet, PDF (29/52 Pages) Agere Systems – QUAD-FET for 10Base-T/100Base-TX/FX

Data Sheet
July 2000
LU3X54FTL
QUAD-FET for 10Base-T/100Base-TX/FX
MII Station Management
Basic Operations
The primary function of station management is to
transfer control and status information about the
LU3X54FTL to a management entity. This function is
accomplished by the MDC clock input, which has a
maximum frequency of 12.5 MHz, along with the MDIO
pin. This pin (112) requires an external 1.5 kΩ pull-up
resistor.
The management interface (MII) uses MDC and MDIO
to physically transport information between the PHY
and the station management entity.
A specific set of registers and their contents (described
in Table 8) defines the nature of the information trans-
ferred across this interface. Frames transmitted on the
MII management interface will have the frame structure
shown in Table 8. The order of bit transmission is from
left to right. Note that reading and writing of the man-
agement register must be completed without interrup-
tion.
Since the LU3X54FTL is a four-channel device, each of
the management registers is duplicated four times as
depicted in the functional block diagram shown in
Figure 1. To select a particular channel [D:A], write to
that channel’s unique PHY address as described in
Table 9.
MII Management Frames
The fields and format for management frames are
described in the following tables.
Table 8. MII Management Frame Format
Read/Write
(R/W)
Pre ST OP PHYADD REGAD TA
DATA
Idle
R
1 . . . 1 01 10 AAAAA RRRRR Z0 DDDDDDDDDDDDDDDD
Z
W
1 . . . 1 01 01 AAAAA RRRRR 10 DDDDDDDDDDDDDDDD
Z
Table 9. MII Management Frames Field Descriptions
Field
Pre
ST
OP
PHYADD
REGAD
TA
DATA
Description
Preamble. The preamble is a series of 32 ones. The LU3X54FTL will accept frames with no pream-
ble. This is indicated by a 1 in register 1, bit 6.
Start of Frame. The start of frame is indicated by a 01 pattern.
Operation Code. The operation code for a read transaction is 10. The operation code for a write
transaction is 01.
PHY Address. The PHY address is 5 bits, allowing for 32 unique addresses. The first PHY address
bit transmitted and received is the MSB of the address. A station management entity, which is
attached to multiple PHY entities, must have prior knowledge of the appropriate PHY address for
each entity. The address 00000 is the broadcast address. This address will produce a match
regardless of the local address.
The LU3X54FTL maps the PHYADD[2:0] to the most significant 3 bits, while the least significant
2 bits address the channel within the LU3X54FTL as follows:
00: Channel A.
01: Channel B.
10: Channel C.
11: Channel D.
Register Address. The register address is 5 bits, allowing for 32 unique registers within each PHY.
The first register address bit transmitted and received is the MSB of the address.
Turnaround. The turnaround time is a 2-bit time spacing between the register address field and the
data field of a frame to avoid drive contention on MDIO during a read transaction. During a write to
the LU3X54FTL, these bits are driven to a 10 by the station. During a read, the MDIO is not driven
during the first bit time and is driven to a 0 by the LU3X54FTL during the second bit time.
Data. The data field is 16 bits. The first bit transmitted and received is bit 15 of the register being
addressed.
Lucent Technologies Inc.
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