LU3X54FTL Datasheet, PDF (37/52 Pages) Agere Systems – QUAD-FET for 10Base-T/100Base-TX/FX

Data Sheet
July 2000
LU3X54FTL
QUAD-FET for 10Base-T/100Base-TX/FX
MII Station Management (continued)
Table 20. MR29—Device-Specific Register 2 (100 Mbits/s Control) Bit Descriptions
Register/Bit¹
Type²
Description
29.15 (LOCALRST)
29.14 (RST1)
29.13 (RST2)
29.12 (100OFF)
R/W Management Reset. This is the local management reset bit. Writing a logic 1 to
this bit will cause register zero and registers 28 and 29 to be reset to their default
values. This bit is self-clearing. Default state is 0.
R/W Generic Reset 1. This register is used for manufacture test only. Default state is 0.
R/W Generic Reset 2. This register is used for manufacture test only. Default state is 0.
R/W 100 Mbits/s Transmitter Off. When this bit is set to 0, it forces TPOUT+[D:A] low
and TPOUT–[D:A] high. This bit defaults to 1.
29.11 (RESERVED)
R/W Reserved. Program to zero.
29.10 (CRS_SEL)
29.9 (LINK_ERR)
29.8 (PKT_ERR)
29.7 (PULSE_STR)
R/W Carrier Sense Select. CRS will be asserted on receive only when this bit is set to
a 1. If this bit is set to logic 0, CRS will by asserted on receive or transmit. This bit
is ORed with the H_DUPLED[B] pin during powerup and reset. Default state is 0.
R/W Link Error Indication. When this bit is a 1, a link error code will be reported on
RXD[3:0] of the LU3X54FTL when RX_ER is asserted on the MII. The specific
error codes are listed in the RXD pin description. If it is 0, it will disable this func-
tion. Default state is 0.
R/W Packet Error Indication Enable. When this bit is a 1, a packet error code, which
indicates that the scrambler is not locked, will be reported on RXD[3:0] of the
LU3X54FTL when RX_ER is asserted on the MII. When this bit is 0, it will disable
this function. Default state is 0.
R/W Pulse Stretching. When this bit is set to 1, the COLED[D:A], TXLED[D:A], and
RXLED[D:A] output signal will be stretched between approximately 42 ms—84 ms.
If this bit is set to 0, it will disable this feature. Default state is 1.
29.6
(ENC_DEC_BYPASS)
R/W Encoder/Decoder Bypass. When this bit is set to 1, the 4B/5B encoder and
5B/4B decoder function will be disabled. This bit is ORed with the TXLED[C] pin
during powerup and reset. Default state is 0.
29.5 (SAB)
R/W Symbol Aligner Bypass. When this bit is set to 1, the aligner function will be dis-
abled. Default state is 0.
29.4
R/W Scrambler/Descrambler Bypass. When this bit is set to 1, the scrambling/
(SCRAM_DESC_BYPASS)
descrambling functions will be disabled. This bit is ORed with the TXLED[B] pin
during powerup and reset. Default state is 0.
29.3 (CARIN_EN)
R/W Carrier Integrity Enable. When this bit is set to a 1, carrier integrity is enabled.
This bit is ORed with the TXLED[D] pin during powerup and reset. Default state
is 0.
29.2 (JAM_COL)
R/W Jam Enable. When this bit is a 1, it enables JAM associated with carrier integrity
to be ORed with COL. Default state is 0.
29.1 (FEF_EN)
29.0 FX_MODE_EN
R/W Far-End Fault Enable. This bit is used to enable the far-end fault detection and
transmission capability. This capability may only be used if autonegotiation is dis-
abled. This capability is to be used only with media which does not support auto-
negotiation. Setting this bit to 1 enables far-end fault detection and generation.
Logic 0 will disable the function. Default state is 0.
R/W FX Mode Enable. When set high, this bit will enable the FX mode (10Base-T and
100Base-TX disabled). When low, it will enable 10Base-T and 100Base-TX mode
(100Base-FX mode disabled). This bit defaults to zero. It is ORed with the FX
mode enable pin.
1. Note that the format for the bit descriptions is as follows: the first number is the register number, the second number is the bit position in the
register, and the name of the instantiated pad is in capital letters.
2. R = read, W = write.
Lucent Technologies Inc.
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