LU3X54FTL Datasheet, PDF (28/52 Pages) Agere Systems – QUAD-FET for 10Base-T/100Base-TX/FX

LU3X54FTL
QUAD-FET for 10Base-T/100Base-TX/FX
Data Sheet
July 2000
Pin Information (continued)
Table 7. Miscellaneous Pins (continued)
Pin
Signal
Type
Description
203
RESET
I Full Chip Reset. Reset must be asserted high for at least five LSCLK
cycles. The LU3X54FTL will come out of reset after 400 µs. LSCLK
must remain running during reset.
199
H_DUPLED[B]/
I/O Half-Duplex LED[B]. When this output is high, it indicates half-duplex
CRS_SEL
mode. When it is low, it indicates full duplex. External buffers are nec-
essary to drive the LEDs. This output is only valid when the link is up.
Carrier Sense Select. At powerup, this pin may be used to select the
mode of CRS operation. When this pin is pulled high through a 4.7 kΩ
resistor, CRS will be asserted on receive activity only. This is the same
function as register 29, bit 10.
This pin has an internal 50 kΩ pull-down resistor for normal mode oper-
ation (default: CRS asserted on transmit or receive activity). This input
and the register bit [29.10] are ORed together during powerup and
reset.
200
H_DUPLED[C]/
I/O Half-Duplex LED[C]. When this output is high, it indicates half-duplex
SERIAL_SEL
mode. When low, it indicates full duplex. External buffers are necessary
to drive the LEDs. This output is only valid when the link is up.
Serial Select. At powerup, this pin may be used to set the
SERIAL_SEL function of register 30, bit 1 for all four channels by pull-
ing it high through a 4.7 kΩ resistor if station management is unavail-
able.
This pin has an internal 50 kΩ pull-down resistor for normal mode oper-
ation (default). This input and the register bit [30.1] are ORed together
during powerup and reset.
54
NC
— No Connect. Do not connect these pins.
28
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