LU3X54FTL Datasheet, PDF (18/52 Pages) Agere Systems – QUAD-FET for 10Base-T/100Base-TX/FX

LU3X54FTL
QUAD-FET for 10Base-T/100Base-TX/FX
Data Sheet
July 2000
Pin Information (continued)
When operating in bused MII mode, 100 Mbits/s data is bused to MII port A, and 10 Mbits/s data is bused to MII
port B.
Table 4. MII/Serial Interface Pins in Bused MII Mode
Pin
Signal
Type
Description
125
TX_CLK25
148
TX_CLK10
O Shared Transmit Clock (25 MHz). 25 MHz clock output in 100 Mbits/s mode.
TX_CLK25 provides timing reference for the transfer of the TX_EN100,
TXD_100, and TX_ER signals that are sampled on the rising edge of
TX_CLK25.
O Shared Transmit Clock (10 MHz). 10 MHz clock output in 10 Mbits/s serial
mode. TX_CLK10 provides timing reference for the transfer of the TX_EN10
and TXD_10 signals that are sampled on the rising edge of TX_CLK10.
109
CRS_10[D:A]
108
107
105
When operating in 10 Mbits/s bused mode, the REF10 input clock must be
used, and the REF_SEL pin must be pulled high through a 4.7 kΩ resistor
(TXLED[A] pin).
O Carrier Sense—10 Mbits/s Mode. When CRS_SEL is low, this signal is
asserted high when either the transmit or receive medium is nonidle. This sig-
nal remains asserted throughout a collision condition. When CRS_SEL is
high, CRS_10 is asserted on receive activity only. CRS_SEL is set via the MII
management interface or the CRS_SEL pin.
99
CRS_100[D:A]/
66
CRS_10/100[D:A]
149
126
154
RX_CLK10
131
RX_CLK25
155
RXD_10
When SMART_MODE_SELECT is asserted, the LU3X54FTL will internally
OR together the CRS_10 and the CRS_100 signals and output them on the
CRS_100 signals.
O Carrier Sense—100 Mbits/s Mode. When CRS_SEL is low, this signal is
asserted high when either the transmit or receive medium is nonidle. This sig-
nal remains asserted throughout a collision condition. When CRS_SEL is
high, CRS_100 is asserted on receive activity only. CRS_SEL is set via the MII
management interface or the CRS_SEL pin.
Carrier Sense—10/100 Mbits/s Smart Mode. When
SMART_MODE_SELECT is asserted, the LU3X54FTL will internally OR
together the CRS_10 and the CRS_100 signals and output them on the
CRS_100 signals.
O Shared Receive Clock. 10 MHz clock output in 10 Mbits/s serial mode.
RX_CLK10 has a worst-case 45/55 duty cycle. RX_CLK10 provides the timing
reference for the transfer of RXD_10 when in the 10 Mbits/s mode. This signal
is sampled on the rising edge of RX_CLK10.
O Shared Receive Clock. 25 MHz clock output in the 100 Mbits/s mode.
RX_CLK25 has a worst-case 45/55 duty cycle. RX_CLK25 provides the timing
reference for the transfer of RX_DV, RXD_100, and RX_ER signals when in
the 100 Mbits/s mode. These signals are sampled on the rising edge of
RX_CLK100.
O Shared Receive Data. Serial data output that is synchronous to the falling
edge of RX_CLK10.
18
Lucent Technologies Inc.