LU3X54FTL Datasheet, PDF (19/52 Pages) Agere Systems – QUAD-FET for 10Base-T/100Base-TX/FX

Data Sheet
July 2000
LU3X54FTL
QUAD-FET for 10Base-T/100Base-TX/FX
Pin Information (continued)
When operating in bused MII mode, 100 Mbits/s data is bused to MII port A, and 10 Mbits/s data is bused to MII
port B.
Table 4. MII/Serial Interface Pins in Bused MII Mode (continued)
Pin
Signal
Type
Description
136
RXD_100[3:0]
135
134
132
O Shared Receive Data. 4-bit parallel data outputs that are synchronous to the
falling edge of RX_CLK25. When RX_ER is asserted high, an error code will
be presented on RXD_100[3:0] where appropriate. The codes are as follows:
s Packet errors, ERROR_CODES = 2h.
s Link errors, ERROR_CODES = 3h (packet and link error codes will only be
repeated if registers [29.9] and [29.8] are enabled).
s Premature end errors, ERROR_CODES = 4h.
60
RX_EN10[D:A]
59
57
56
s Code errors, ERROR_CODES = 5h.
I Receive Enable—10 Mbits/s Mode. When SMART_MODE_SELECT is not
enabled and RX_EN10 is driven high, its channel’s data and clock (RXD0 and
RX_CLK) are driven onto the shared serial bus. If the individual channel is not
configured for 10 Mbits/s mode, this input will be ignored. When RX_EN10s
are all set low, the serial bus will float.
Note: Care should be taken that no more than one RX_EN is asserted at a
time.
110
RX_EN100[D:A]/
78
RX_EN10/100[D:A]
161
138
When SMART_MODE_SELECT is enabled, these pins are ignored.
I Receive Enable—100 Mbits/s Mode. When SMART_MODE_SELECT is not
enabled and RX_EN100 is driven high, its channel’s data, clock, and receive
data valid signals (RXD_100, RX_DV, RX_ER, and RX_CLK25) are driven
onto the shared MII bus. If the individual channel is not configured for
100 Mbits/s mode, this input will be ignored. When RX_EN100s are all set low,
the MII bus will float.
128
RX_DV
130
RX_ER
139
TXD_10
120
TXD_100[3:0]
119
117
116
Note: Care should be taken that no more than one RX_EN is asserted at a
time.
Receive Enable—10/100 Mbits/s Smart Mode. When
SMART_MODE_SELECT is asserted and RX_EN100 is driven high, its chan-
nel’s data, clock, and receive data valid signals [RXD, RX_ER (100 Mbits/s
only), RX_DV (100 Mbits/s only), and RX_CLK] are driven onto the shared bus
corresponding to the speed of the channel.
O Shared Receive Data Valid. When this pin is driven high, it indicates that the
LU3X54FTL is recovering and decoding valid nibbles on RXD[3:0] and that the
data is synchronous with RX_CLK. RX_DV is synchronous with RX_CLK. This
pin is not used in serial 10 Mbits/s mode.
O Shared Receive Error. When asserted high, it indicates that the LU3X54FTL
has detected a coding error in the frame presently being transferred. RX_ER is
synchronous with RX_CLK25. This signal is not used in 10 Mbits/s mode.
I Shared Transmit Data. 10 Mbits/s serial input synchronous with TX_CLK10.
I Shared Transmit Data. 4-bit parallel input synchronous with TX_CLK25.
Lucent Technologies Inc.
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