LU3X54FTL Datasheet, PDF (23/52 Pages) Agere Systems – QUAD-FET for 10Base-T/100Base-TX/FX

Data Sheet
July 2000
LU3X54FTL
QUAD-FET for 10Base-T/100Base-TX/FX
Pin Information (continued)
Table 7. Miscellaneous Pins
Pin
Signal
81
CKREF
184
ATEST[B:A]
183
197
AUTO_EN
1, 7,
11, 14,
18, 22,
24, 26,
29, 31,
35, 39,
41, 45,
49, 58,
64, 73,
79, 82,
86, 91,
97, 106,
115, 118,
124, 133,
141, 147,
156, 163,
177, 178,
181, 182,
186, 208
4, 8, 12,
15, 19,
23, 28,
30, 34,
38, 40,
44, 48,
52, 77,
80, 83,
94, 111,
144, 167,
172, 179,
180, 185,
195, 202
61, 69,
102, 121,
129, 137,
152, 160
196
25
13
42
GND/VSS
VDD
VDD3
3ST_EN
BGREF[1:0]
ISET_10
Type
Description
I Clock Reference. Connect this pin to a 1 nF ± 10% capacitor to
ground.
O Reserved. For normal operation, leave these pins unconnected.
I Autonegotiation Enable. When this pin is high, autonegotiation is
enabled. Pulsing this pin will cause autonegotiation to restart. This
input has the same function as register 0, bit 12. This input and the reg-
ister bit are ANDed together.
PWR Ground. (38 pins.)
PWR VDD. 5.0 V ± 5% power supply (27 pins.)
PWR VDD3. 3.3 V ± 5% or 5.0 V ± 5% power supply (8 pins.)
I 3-State Enable. When this pin is high, all digital outputs will be
3-stated. For normal operating conditions, pull this pin low.
I Band Gap Reference. Connect these pins to a 24.9 kΩ ± 1% resistor
to ground. The parasitic load capacitance should be less than 15 pF.
I Current Set 10 Mbits/s. An external resistor (22.1 kΩ) is placed from
this pin to ground to set the 10 Mbits/s TP driver transmit output level.
Lucent Technologies Inc.
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