Z90251 Datasheet, PDF (88/97 Pages) Zilog, Inc. – eZVision 200 Television Controllers with OSD

Z90255 ROM and Z90251 OTP
32 KB Television Controller with OSD
80
10 Analog-to-Digital Converter
The Z90255 is equipped with a 4-bit flash analog-to-digital converter (ADC) that
can be used as either three or four bit configurations. There are four multiplexed
analog-input channels. There are two register addresses, one for 3-bit (Table 70)
ADC (3ADC_DTA: 00h: Bank C), and one for 4-bit (Table 71)
ADC (4ADC_DTA: 01h: Bank F). Because no default is set, system software
must configure the control register for the preferred ADC.
Converted 3-bit data is available as bits 0, 1, and 2 of the 3-bit ADC data register.
Converted 4-bit data is available as bits 0, 1, 2, and 3 of the 4-bit ADC data
register.
Figure 21 illustrates four input pins (P60/ADC3, P61/ADC2, P41/ADC1, and
P62/ADC0) which function as analog-input channels and as digital I/O ports. To
support the analog function, the digital ports must be configured as analog
through software. Analog/digital selection is controlled by bits 4 and 3 of the 3-bit
ADC Data Register, and by bits 5 and 4 of 4-bit ADC Data Register.
• If ADC Input Selection equals 00, ADC0 is selected; this value is the default
following POR.
• If ADC Input Selection equals 01, ADC1 is selected.
• If ADC Input Selection equals 10, ADC2 is selected.
• If ADC Input Selection equals 11, ADC3 is selected.
Sampling occurs at one-eighth of an ADC-clock tick. One ADC-clock tick equals
one-half, one-third, or one-quarter of a system-clock (SCLK) tick, as set by
3ADC_DTA(6,5) for 3-bit or 4ADC_DTA (7,6) for 4-bit. If ADC speed bits are
set to 00, the ADC is not operative; this is the default value following POR. If these
bits equal 01, ADC speed is based on one-half of a system-clock tick, SCLK/2. If
these bits equal 10, ADC speed is based on one-third of a system-clock tick,
SCLK/3. If these bits equal 11, ADC speed is based on one-quarter of a system-
clock tick, SCLK/4.
PS001301-0800