Z90251 Datasheet, PDF (78/97 Pages) Zilog, Inc. – eZVision 200 Television Controllers with OSD

Z90255 ROM and Z90251 OTP
32 KB Television Controller with OSD
70
Bit/
Field
Reserved
P47/
PWM 10
P46/
PWM9
P45/
PWM 8
P44/
PWM 7
Reserved
Bit
Position
7, 6
5
4
3
2
1, 0
R/W Value Description
R
Return 1
W
No effect
R/W 0 Select PWM 10
1 Select P47 - POR
R/W 0 Select PWM 9
1 Select P46 - POR
R/W 0 Select PWM 8
1 Select P45 - POR
R/W 0 Select PWM 7
1 Select P44 - POR
R
Return 1
W
No effect
9.2 PWM1 through PWM11
Two data registers (PWM11H and PWM11L) hold the 14-bit PWM11 ratio. If PWM6
is configured to 14-bit, two data registers (PWM6H and PWM6L) hold the 14-bit
PWM6 ratio. The upper 7 bits control the width of the distributed pulse. The lower
7 bits distribute the minimum resolution pulse in the various time slots. Using this
technique, the pseudo-repetition of frequency is raised up to 128 times faster than
ordinary pulse width modulation.
There are 128 time slots which start from time slot 7Fh to 0h because a 14-bit
binary down counter is used. When the glitch exceeds 127 pulses, the upper 7
bits take precedence and fill 128 pulses of the same width in different locations.
Generating the pulse-train output requires the following equation: Time slot (Fts)
and one cycle of frequency (F14).
Fdp (Distribution pulse frequency)=XTAL/128 (Hz)
Fts (Time slot frequency) = XTAL/128 (Hz)
F14 (a cycle/frequency) = XTAL /16384 (Hz)
When the 6-bit data is 00h, the PWM output is Low. The maximum value is 3Fh
and emits High DC-level output.
A selected PWM cycle/frequency is shown in the following equation:
F6 (a cycle/frequency) = XTAL/16/64 (Hz)
PS001301-0800