Z90251 Datasheet, PDF (28/97 Pages) Zilog, Inc. – eZVision 200 Television Controllers with OSD

Z90255 ROM and Z90251 OTP
32 KB Television Controller with OSD
20
External Clock Divide-by-Two This bit can eliminate the oscillator divide-by-
(bit 1)
two circuitry. When this bit is 0, the System
Clock (SCLK) and Timer Clock (TCLK) are
equal to the external clock frequency divided by
two. The SCLK/TCLK is equal to the external
clock frequency when this bit is set (D1=1).
Using this bit together with D7 of PCON helps
lower EMI (D7 (PCON) =0, D1 (SMR) =1). The
default setting is zero.
Stop-Mode Recovery Source These three bits specify the wake-up source of
(bits 2, 3, and 4)
the Stop-Mode recovery.
Figure 7 illustrates Stop Mode Recovers Source/Level Select.
Table 7 Stop Mode Recovery Source
Bits
Operation
4 32
0 00
0 01
0 10
1 01
1 10
1 11
Description of Action
POR and/or external reset recovery
P63 transition
P62 transition (not in Analog Mode)
P27 transition
Logical NOR of P20 through P23
Logical NOR of P20 through P27
Stop Mode Recovery Delay
Select (bit 5)
This bit, if High, enables the T_POR Reset delay
after Stop Mode Recovery. The default
configuration of this bit is 1. If the fast wake up
is selected, the Stop Mode Recovery source is
kept active for at least 5 TpC.
PS001301-0800