Z90251 Datasheet, PDF (7/97 Pages) Zilog, Inc. – eZVision 200 Television Controllers with OSD

Z90255 ROM and Z90251 OTP
32 KB Television Controller with OSD
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List of Tables
1 Z90255 Production Device Pin Assignment ............................................... 6
2 Single-Purpose Pin Descriptions ................................................................ 7
3 Multiplexed Pin Descriptions....................................................................... 8
4 Register File Map...................................................................................... 13
5 Watch-Dog Timer Mode Register 0Fh: Bank F ......................................... 15
6 Stop Mode Recovery (SMR) Register 0Bh: Bank F (SMR) ...................... 19
7 Stop Mode Recovery Source .................................................................... 20
8 OSD Control Register 00h:Bank A (OSD_CNTL)..................................... 22
9 Vertical Position Register 01h:Bank A (VERT_POS) ............................... 24
10 Horizontal Position Register 02h:Bank A (HOR_POS) ............................. 25
11 Second Color Control Register 07h:Bank A (SNDCLR_CNTRL) ............. 26
12 Second Color Register 08h:Bank A (SNDCLR)........................................ 26
13 Mesh Column Start Register 04h: Bank F (MC_St) .................................. 29
14 Mesh Column End Register 05h: Bank F (MC_End) ................................ 30
15 Mesh Row Enable Register 06h: Bank F (MR_En) .................................. 30
16 Mesh Control Register 07h: Bank F (MC_Reg) ........................................ 31
17 BGR Mesh Colors ..................................................................................... 33
18 Fade Position Register 1 05h: Bank A (FADE_POS1) ............................. 35
19 Fade Position Register 2 06h: Bank A (FADE_POS2) ............................. 35
20 Row Space Register 04h: BankA (ROW_SPACE) ................................... 36
21 RGB Colors ............................................................................................... 40
22 Display Attribute Register 03h: Bank A (DISP_ATTR) ............................. 41
23 VRAM Structure and Memory Map ........................................................... 43
24 Color Palette Selection Bits ...................................................................... 45
25 Color Index Register 09h: Bank C (CLR_IDX).......................................... 45
26 Color Palette 0 Register 09h: Bank A (CLR_P0) ...................................... 46
27 Color Palette 1 Register 0Ah: Bank A (CLR_P1) ...................................... 46
28 Color Palette 2 Register 0Bh: Bank A (CLR_P2) ...................................... 47
29 Color Palette 3 Register 0Ch: Bank A (CLR_P3) ..................................... 47
30 Color Palette 4 Register 0Dh: Bank A (CLR_P4) ..................................... 47
31 Color Palette 5 Register 0Eh: Bank A (CLR_P5) ...................................... 48
32 Color Palette 6 Register 0Fh: Bank A (CLR_P6) ...................................... 48
33 Row Attribute Register (ROW_ATTR) ...................................................... 49
34 HV Interrupt Status Register 07h: Bank C (INT_ST) ................................ 50
35 Master I2C Control Register 0Ch: Bank C (I2C_CNTL) ........................... 54
36 Master I2C Command Register 0Bh: Bank C (I2C_CMD) ........................ 55
PS001301-0800