Z90251 Datasheet, PDF (25/97 Pages) Zilog, Inc. – eZVision 200 Television Controllers with OSD

Z90255 ROM and Z90251 OTP
32 KB Television Controller with OSD
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execute a NOP instruction (opcode = FFh) immediately before the Halt instruction
(opcode 7Fh), that is,
FF NOP
7F Halt
;clear the instruction pipeline
;enter Halt Mode
The Halt Mode is exited by interrupts, generated either externally or internally.
When the interrupt service routine is completed, the user program continues from
the instruction after Halt.
The Halt Mode can also be exited via a POR/Reset activation or a Watch-Dog
Timer (WDT) timeout. In this case, program execution restarts at the reset-restart
address 000Ch.
To reduce power consumption further in the Halt Mode, the Z90255 and Z90251
allow dynamic internal clock scaling. Clock scaling can be accomplished on the fly
by reprogramming bit 0 and/or bit 1 of the Stop-Mode Recovery register (SMR).
Note: _{Internal clock scaling directly effects Counter/Timer operation:}
adjustment of the prescaler and downcounter values might be
required.
4.2 Stop Mode Operation
The Stop Mode provides the lowest possible device standby current. This
instruction turns off the on-chip oscillator and internal system clock.
To enter the Stop Mode, the instruction pipeline must be flushed first to avoid
suspending execution in mid-instruction. To do this, the application program must
execute a NOP instruction (opcode=FFh) immediately before the Stop instruction
(opcode=6Fh), that is,
FF NOP
6F Stop
;clear the instruction pipeline
;enter Stop Mode
The Stop Mode is exited by any one of the following resets: Power-On Reset
activation, WDT timeout, or a Stop-Mode Recovery source. When reset is
generated, the processor always restarts the application program at address
000Ch.
POR/Reset activation is present on the Z90255 and Z90251 and is implemented
as a reset pin and/or an on-chip power on reset circuit.
When the WDT is configured to run during Stop mode, the WDT timeout
generates a Reset ending Stop Mode.
PS001301-0800