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Z90251 Datasheet, PDF (57/97 Pages) Zilog, Inc. – eZVision 200 Television Controllers with OSD
Z90255 ROM and Z90251 OTP
32 KB Television Controller with OSD
49
Row Attribute Register
The Row Attribute Register (Table 33) is mapped to VRAM, as shown in Table 20.
This register controls row background and foreground display. If the Color Index is
set to 000h, the display color is read from the Row Attribute Register.
Table 33 Row Attribute Register (ROW_ATTR)
Bit
7
6
5
4
3
2
1
0
R/W
Reset
R/W R/W R/W R/W R/W R/W R/W R/W
x
x
x
x
x
x
x
x
Note: R = Read W = Write X = Indeterminate
Bit/
Field
Row Foreground
Enable
Row Foreground
Color
Row Background
Enable
Row Background
Color
Bit
Position R/W Value Description
7
6, 5, 4
3
2, 1, 0
R/W 0 Row Foreground Color displayed
1 Row Foreground color disabled
R/W
Defines the Character Color R, G, B,
respectively
R/W 0 Row Background Color disabled
1 Row Background color displayed
R/W
Defines the Row Background Color R,
G, B, respectively
5.10 HV Interrupt Processing
An interrupt is issued at the beginning of a row and at the leading edge of the
VSYNC signal. The leading edge of the first HSYNC of a row constitutes the
beginning of a row. The Z90255 software tracks this cycle as two recurring events,
the Horizontal (HSYNC) Interrupt and the Vertical (VSYNC) Interrupt.
A VSYNC interrupt marks the time for displaying a new field of a TV frame.
Displaying subsequent rows coincides with the issuance of the HSYNC interrupt.
The interrupts mark the time when displaying a row or start of a field is to occur.
Each text row is comprised of 18 scan lines. Each scan line takes 63.5 µs to be
displayed. So, 1143 µs is the amount of time available to change programming for
the next row. Double-size and double-height characters span 36 scan lines,
PS001301-0800