Z90251 Datasheet, PDF (75/97 Pages) Zilog, Inc. – eZVision 200 Television Controllers with OSD

Z90255 ROM and Z90251 OTP
32 KB Television Controller with OSD
67
Bit/
Field
Bit
Position
R/W Value Description
CAP Glitch
3, 2
R/W
00 Glitch Filter Disabled
01 <2SCLK Filtered Out
10 <8SCLK Filtered Out
11 <16SCLK Filtered Out
CAP Speed 1, 0
R/W
00 SCLK/32
01 SCLK/4
10 SCLK/8
11 SCLK/16
Bit 6 resets the IR Capture Timer. To stop the timer, set this bit to 1. To start the
timer, set the bit to 0.
Bits 5 and 4 set the IR Capture Edge. The rising edge, the falling edge, or both
edges of an input signal can be used as the source of IR interrupts. If both edges
are set as interrupt sources, Timer Control Register 0 (TCR0: 01h: Bank C)
must be read and checked by the Interrupt Service Routine (ISR) in order to
identify which edge was captured.
Bits 3 and 2 contain a time constant used in a digital filter to process the IR
Capture module in order to prevent errors.
Bits 1 and 0 set the IR Capture Counter to one of four different speeds.
The IR capture counter is driven by the clock generated by dividing the system
clock in the Z90255.
Table 52 IR Capture Register 0 03h: Bank C (IR_CP0)
Bit
7
6
5
4
3
2
1
0
R/W
Reset
R
R
R
R
R
R
R
R
0
0
0
0
0
0
0
0
Note: R = Read W = Write X = Indeterminate
Bit/
Field
Bit
Position
IR Capture Register 0 7,6,5,4,3,2,1,0
R/W Value Description
R
Reading Low Byte of IR
Capture Data
PS001301-0800