Z90251 Datasheet, PDF (61/97 Pages) Zilog, Inc. – eZVision 200 Television Controllers with OSD

Z90255 ROM and Z90251 OTP
32 KB Television Controller with OSD
53
6 Z90255 I2C Master Interface
The Z90255 has a hardware module which supports the I²C Master interface. Bus
arbitration and MastersÕ arbitration logic is NOT implemented; in other words, the
Z90255 is designed for a Single Master application.
The I²C interface can be configured to run at four different transfer speeds defined
by bits (1,0) in the I²C Control Register (I²C_CNTL: 0Ch, Bank:C).
To circumvent possible problems on both DATA and SCLK lines, digital filters with
time constant equal to 3T_sclk are implemented on all inputs of the I²C bus
interface. The Z90255 has two separate I²C busses which share the same I²C
state machine.
The I²C module is enabled by setting bit (2) in the I2C_CNTL register to 1(see
Figure 17). This bit blocks out I²C logic if it is set to 0. To prevent switching the I²C
bus during activation, bits (7,6) of the Port 2 Data Register for I²C selection 1 (bits
(5,4) of Port 2 Data Register for I²C selection 0) should be set to 1 before the I²C
module is enabled.
Notes: 1
When the I²C module is enabled, pins used as I²C must be
configured as output in the Port 2 Mode Register (P2M:
F6h). If P27/P26 or P25/P24 are used as I²C pins, then
these pins are automatically set to open-drain mode.
2 Port 2 must be configured in standard drive mode (PCON:
00h: Bank F) when the I²C interface is active.
P2CNTL (0)
P2M 1 = Input
0 = Output
I²C DATA (Output)
1
V_CC
PAD
P2 (Output)
0S
I²C Selection
P2 (Input)
I²C DATA (Input)
I²C Enable
For I²C
Figure 17 Bidirectional Port Pin Pad Multiplexed with I2C Port
PS001301-0800