Z90251 Datasheet, PDF (26/97 Pages) Zilog, Inc. – eZVision 200 Television Controllers with OSD

Z90255 ROM and Z90251 OTP
32 KB Television Controller with OSD
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Note: ^{Stop-Mode Recovery (SMR) by the WDT increases the Stop}
Mode standby current (ICC2). This is because the internal RC
oscillator is running to support this recovery mode.
The Z90255 and Z90251 have Stop-Mode Recovery (SMR) circuitry. Two SMR
methods are implemented, a single-fixed input pin or a flexible, programmable set
of inputs. The Z8-base product specification should be reviewed to determine the
SMR options available.
In simple cases, a Low level applied to input pin P27 triggers an SMR. To use this
mode, pin P27 (I/O Port 2, bit 7) must be configured as an input before entering
Stop Mode. The Low level on P27 must meet a minimum pulse width TWSM.
Some microcontrollers provide multiple SMR input sources. The SMR source is
selected via the SMR Register.
Note: Using specialized SMR modes (P27 input or SMR register
based) or the WDT timeout (only when in the Stop Mode)
provides a unique reset operation. Some control registers are
initialized differently for a SMR/WDT triggered POR than a
standard reset operation.
Note: The Stop Mode current (ICC2) is minimized when
- V_CC is at the low end of the device operating range
- WDT is Off in Stop Mode
- Output current sourcing is minimized
- All inputs (digital and analog) are at the low or high rail voltages
4.3 STOP Mode Recovery Register
The STOP Mode Recovery Register register selects the clock divide value and
determines the mode of Stop Mode Recovery. All bits are Write-Only, except bit 7
which is Read-Only. Bit 7 is a flag bit that is hardware set in a Stop Mode
Recovery condition, and reset by a power-on cycle. Bit 6 controls whether a Low
level or a High level is required from the recovery source. Bit 5 controls the reset
delay after recovery. Bits 2, 3, and 4, of the SMR register, specify the source of the
Stop-Mode Recovery signal. Bits 0 and 1 control internal clock divider circuitry.
The SMR is located in bank F of the expanded register file at address 0Bh.
Table 6 contains Stop Mode Recovery (SMR) Register bit descriptions.
PS001301-0800