Z90251 Datasheet, PDF (23/97 Pages) Zilog, Inc. – eZVision 200 Television Controllers with OSD

Z90255 ROM and Z90251 OTP
32 KB Television Controller with OSD
15
3 Watch-Dog Timer (WDT)
The Watch-Dog Timer (WDT) is driven by an internal RC oscillator. Therefore
accuracy is dependent on the tolerance of the RC components. Table 5 describes
the Watch-Dog Timer Mode register bits.
Table 5 Watch-Dog Timer Mode Register 0Fh: Bank F
Bit
7
6
5
4
3
2
1
0
R/W
W
W
W
W
W
W
W
W
Reset
0
0
0
0
0
1
0
1
Note: R = Read W = Write X = Indeterminate
Bit/
Field
reserved
WDT During Stop
WDT During Halt
WDT TAP
Bit
Position
7-4
3
2
1, 0
R/W Value Description
W 0 Must be 0
W 0 Off
1 On POR
W 0 Off
1 On POR
W 00 6 msec
01 12 msec POR
10 24 msec
11 96 msec
WDT During Halt Mode (T2)
Bit 2 determines if the WDT is active during Halt Mode. A 1 value indicates active
during Halt. The default is 1. A WDT timeout during Halt Mode resets control
registers and ports to their default reset conditions.
Bit 3 determines if the WDT is active during Stop mode. A 1 value indicates
active during Stop mode. A WDT timeout during Stop mode resets control
registers and ports to their default reset conditions.
Bits 4, 5, 6 and 7 are reserved and must be cleared to 0.
The WDTMR register is accessible only during the first 60 processor cycles from
the execution of the first instruction after Power-On Reset, Watch-Dog Reset, or a
PS001301-0800