Z84C90_12 Datasheet, PDF (54/56 Pages) Zilog, Inc. – KIO Serial/Parallel Counter/Timer

Z84C90 KIO Serial/Parallel Counter/Timer
Product Specification
47
Precautions & Limitations
The following issues describe the possible limitations and resulting workarounds when
working with Revision A of the Z84C90 KIO Peripheral.
Daisy-Chain
If the KIO has an interrupt pending during an Interrupt Acknowledge cycle, the KIO
misses the status of the IE1 pin. As a result, vector contention is produced if there is a
higher interrupting device. However, operation is as expected if only one device is in the
system.
Workaround: There is no problem if the application has only one peripheral in the daisy
chain. For two or more peripherals in the system, a hardware workaround circuit is
required. Please contact your local Zilog representative to obtain more information.
Reset
KIO requires the M1 signal to exit from a Reset state. If the M1 signal is not received, the
KIO cannot be programmed. This problem does not exist for users of the Z80 CPU.
Workaround: If the CPU is other than a Z80 CPU, an M1 signal is required to exit
RESET status. Otherwise, the KIO cannot be programmed.
Port C
When Port C is used as a parallel I/O (and not as modem signals for an SIO ) and there is a
status change on PC1 or PC6, the status of SYNCA or SYNCB (SIO cell) also changes.
Workaround: Before using Port C as a parallel port, set the SIO modem signal mode back
to Port C. This procedure avoids the problem.
Interrupt Acknowledge Cycle
The KIO modifies the contents of the KIO Control Register (specifically, the KIO modi-
fies the daisy-chain configuration) if the CE pin is active during the Interrupt Acknowl-
edge cycle (assuming other conditions are satisfied).
This problem can occur under the following narrowly-defined conditions:
• The CE signal is active throughout the Interrupt Acknowledge cycle
• The address on the bus, A3–A0, is 110b
• Bit D3 is 1
PS011804-0612
Precautions & Limitations