Z84C90_12 Datasheet, PDF (33/56 Pages) Zilog, Inc. – KIO Serial/Parallel Counter/Timer

Z84C90 KIO Serial/Parallel Counter/Timer
Product Specification
26
D7 D6 D5 D4 D3 D2 D1 D0
Note: *Also SDLC address field.
Sync bit 0
Sync bit 1
Sync bit 2
Sync bit 3
Sync bit 4
*
Sync bit 5
Sync bit 6
Sync bit 7
Figure 28. SIO Write Register 6
D7 D6 D5 D4 D3 D2 D1 D0
Sync bit 8
Sync bit 9
Sync bit 10
Sync bit 11
Sync bit 12
*
Sync bit 13
Sync bit 14
Sync bit 15
Note: For SDLC, these bits must be programmed to 01111110 for flag recognition.
Figure 29. SIO Write Register 7
PIA Registers
The PIA port can be configured for any combination of input and output bits. The direc-
tion is controlled by writing to the PIA Control Register. A 1 written to a bit position indi-
cates that the respective bit should be an input (see Figure 30). All bits are inputs upon
reset.
PS011804-0612
Register Programming