Z84C90_12 Datasheet, PDF (49/56 Pages) Zilog, Inc. – KIO Serial/Parallel Counter/Timer

Z84C90 KIO Serial/Parallel Counter/Timer
Product Specification
42
Table 5. AC Characteristics of the Z84C90 (Continued)
8 MHz
10MHz^1,6 12.5MHz^1,6
No. Symbol
Parameter
Min Max Min Max Min Max U/M
SIO Timing (continued)
70 TsSYNCf
SYNC Fall to RxC Rise Setup  –100
–100
–100
ns
(RxCr)
(External Sync Mode)
71 TdCf(IEOr) Clock Fall to IEO Rise Delay
90
75
60 ns
72 TdCf(IEOf) Clock Fall to IEO Fall Delay
110
90
75 ns
73 ThDI(M1r,Rdr) Data Hold Time to M1 Rise or RD 0
0
0
ns
Rise
74 TsM1/RD(C) Setup time for M1 and RD to clock 20
20
20
ns
Rising (with Data Valid)
Notes:
1. Maximum SIO data rate is f_CLOCK ÷ by 5, in which f_CLOCK = 1 ÷ T_CC.
2. For a Z80 CPU operating above 8MHz, one wait state is required to meet this parameter.
3. These daisy chain parameters include contributions from the PIO, SIO and CTC cells, and vary slightly
depending on how they are ordered by the KIO Command Register.
4. Counter mode only; when using a cycle time less than 3 TcC, parameter #37 must be met.
5. Units are TcC.
6. If the CPU is a Z80 CPU and if it is required to have multiple Z80 peripherals in the system, then the time period
between M1 to IORQ must be extended.
7. Any open-drain output must add a Register-Capacitor (RC) time constant to the specification value.
Figure 42 offers a visual representation of the daisy chain sequence; Table 6 lists 8 MHz,
10 MHz and 12 MHz daisy chain parameters.
IEI
Input
Buffer
Device
#1
Device
#2
Device
#3
Figure 42. Internal Daisy Chain Configuration
Output
Buffer
IEO
PS011804-0612
AC Characteristics