Z84C90_12 Datasheet, PDF (27/56 Pages) Zilog, Inc. – KIO Serial/Parallel Counter/Timer

Z84C90 KIO Serial/Parallel Counter/Timer
Product Specification
20
D7 D6 D5 D4 D3 D2 D1 D0
TC7
TC0
TC6
TC1
TC5
TC2
TC4
TC3
Figure 17. CTC Time Constant Word
Interrupt Vector Word. If one or more of the CTC channels have interrupts enabled, the
Interrupt Vector Word must be programmed into the CTC Register. Only the five most
significant bits of this word are programmed, and bit D0 must be 0. Bits D2–D1 are auto-
matically modified by the CTC channel when it responds with an interrupt vector. See
Figure 18.
Supplied
by user
D7 D6 D5 D4 D3 D2 D1 D0
0 = Interrupt vector word
1 = Control word
Channel identifier
(automatically inserted by CTC)
0 0 = Channel 0
0 1 = Channel 1
1 0 = Channel 2
1 1 = Channel 3
Figure 18. CTC Interrupt Vector Word
SIO Registers
These registers apply to channels A and B (additionally, see the Register Address Decod-
ing for the KIO section on page 13). The Command/Status Register initially functions as
Write Register 0 (WR0) and operates as a pointer to the read registers or to the write regis-
ters. The read register for Write Register 0 is RR0. The read registers for Write Register 1
and Write Register 2 are RR1 and RR2, respectively.
For more information about these SIO registers, please consult the Z80 CPU Peripherals
User Manual (UM0081).
PS011804-0612
Register Programming