Z84C90_12 Datasheet, PDF (35/56 Pages) Zilog, Inc. – KIO Serial/Parallel Counter/Timer

Z84C90 KIO Serial/Parallel Counter/Timer
Product Specification
28
Command Register B. Writing a 1 to a particular command bit location of the KIO gen-
erates a RETI sequence internally. Every time a RETI is required, a 1 is written to this bit
to allow software control of the RETI.
Programming of this Feature. This revision has one newly assigned register at Register
Address 15 (this location is reserved on the original version). The bit assignments for this
register are shown in Figure 32.
D7 D6 D5 D4 D3 D2 D1 D0
Software RETI (write only)
Reserved
Figure 32. KIO Register 15: KIO Command Register B
Writing a 1 to the bit D0 location of this register enables the KIO to simulate a RETI
sequence. Writing a 0 to this bit yields no effect. The upper 7 bits of this register (D7–D1)
are reserved and should be programmed to 0. If this register is read, unpredictable data is
returned.
Notes: After writing a 1 to this bit, 8 clock cycles of access recovery time is required before addi-
tional access to the KIO can occur. If accessing the KIO within this recovery period, the
KIO ignores the transaction on the bus.

When simulating RETI, the status of the IEI pin is ignored with an internally forced H. If
there are other peripherals on the upper interrupt daisy chain, caution must be exercised.
PS011804-0612
Z84C90 KIO: Enhanced Version