Z84C90_12 Datasheet, PDF (20/56 Pages) Zilog, Inc. – KIO Serial/Parallel Counter/Timer

Z84C90 KIO Serial/Parallel Counter/Timer
Product Specification
13
Hunt status bit for their respective serial channels, but serve no other purpose. These pins
are multiplexed with Port C, bits 6 and 1, respectively.
TxCA, TxCB. Transmit Clock (inputs, active Low). These clocks are used to transmit data
from the transmit shift register for their serial channels. Data is transmitted on the falling
edge of the clock.
TxDA, TxDB. Transmit Data (outputs, active High). These pins are the output data pins
from the transmitter for their serial channels.
WT/RDYA, WT/RDYB. Wait/Ready (outputs, open-drain when programmed as Wait;
tristated when programmed as Ready). These pins may be programmed as Ready lines for
a DMA controller or Wait lines for interfacing to a CPU. As a Ready line, these pins indi-
cate (when active Low) that the transmitter or the receiver requests a transfer between the
serial channel and the DMA. As a Wait line, these pins dictate (when Low) that the CPU
must wait until the transmitter or receiver can complete the requested transaction. These
pins are multiplexed with Port C, bit 7 and 0, respectively.
XTALI. Crystal/Clock Connection. (input).
XTALO. Crystal Connection. (output).
ZC/TO0–ZC/TO3. Zero count/Time-Out (outputs, active High). These four pins are out-
puts from the four counter/timer channels of the KIO. Each pin pulses High when its cor-
responding downcounter reaches 0.
Register Address Decoding for the KIO
Address lines A0–A3 determine which one of the 16 control registers is being accessed.
Table 2 shows the address decoding of each of the KIO control registers; also see Figure 9
on page 15.
Table 2. KIO Registers
Address
A3 A2 A1 A0
Register 0: PIO Port A Data
0
0
0
0
Register 1: PIO Port A Command
0
0
0
1
Register 2: PIO Port B Data
0
0
1
0
Register 3: PIO Port B Command
0
0
1
1
Register 4: CTC Channel 0
0
1
0
0
Note: Additionally, IORQ and CS must be Low. Registers are written to or read from by the
CPU, applying a 1 or a 0 respectively on the RD pin.
PS011804-0612
Register Address Decoding for the KIO