Z84C90_12 Datasheet, PDF (17/56 Pages) Zilog, Inc. – KIO Serial/Parallel Counter/Timer

Z84C90 KIO Serial/Parallel Counter/Timer
Product Specification
10
Pin Descriptions
A0–A3. Address bus (inputs). Used to select the port/register for each bus cycle.
ARDY, BRDY. Port Ready (outputs, active High). These signals indicate that the port is
ready for a data transfer. In Mode 0, the signal indicates that the port has data available to
the peripheral device. In Mode 1, the signal indicates that the port is ready to accept data
from the peripheral device. In Mode 2, ARDY indicates that Port A has data available for
the peripheral device, but that the data is not be placed onto PA0–PA7 until the ASTB sig-
nal is Active. BRDY indicates that Port A is able to accept data from a peripheral device.
Note: Port B does not support Mode 2 operation and can only be used in Mode 3 when Port A is
programmed for Mode 2. BRDY is not associated with Port B when it is operating in
Mode 3.
ASTB, BSTB. Port Strobe (inputs, active Low). These signals indicate that the peripheral
device has performed a transfer. In Mode 0, the signal indicates that the peripheral device
has accepted the data present on the port pins. In Mode 1, the signal causes the data on the
port pins to be latched onto Port A. In Mode 2, ASTB Low causes the data in the output
data latch of Port A to be placed onto the Port A pins. BSTB Low causes the data present
on the Port A pins to be latched into the Port A input data latch. The end of the current
transaction is noted by the rising edge of these signals.
Note: Port B does not support Mode 2 operation, and can only be used in Mode 3 when Port A is
programmed for Mode 2. BSTB is not associated with Port B when it is operating in Mode 3.
CLK/TRG0–CLK/TRG3. External Clock/Timer Trigger (inputs, user-selectable active
High or Low). These four pins correspond to the four counter/timer channels of the KIO.
In Counter mode, each active edge causes the downcounter to decrement. In Timer mode,
an active edge starts the timer.
CLKOUT. Clock Out (output). This output is a divide-by-two of the oscillator (XTAL)
input.
CLOCK. System Clock (input). This clock must be the same as (or a derivative of) the
CPU clock. If the CLKOUT is to be used as the system clock, then these two pins must be
connected together.
PS011804-0612
Pin Descriptions