Z84C90_12 Datasheet, PDF (18/56 Pages) Zilog, Inc. – KIO Serial/Parallel Counter/Timer

Z84C90 KIO Serial/Parallel Counter/Timer
Product Specification
11
CS. Chip Select (input, active Low). Used to activate the internal register decoding mech-
anism and allow the KIO to perform a data transfer to/from the CPU.
CTSA, CTSB. Clear to Send (inputs, active Low). These signals are modem control sig-
nals for the serial channels. When programmed for Auto Enable, a Low on these pins
enables their respective transmitters. If not programmed as Auto Enable, these pins may
be used as general-purpose input signals.
D0–D7. Data Bus (bidirectional, active High, tristated). Used for data exchanges between
the CPU and the KIO for programming and data transfer. The KIO also monitors the data
bus for Return from Interrupt (RETI) instructions to maintain its Interrupt Under Service
(IUS) status.
DCDA, DCDB. Data Carrier Detect (inputs, active Low). These signals are modem control
signals for the serial channels. When programmed for Auto Enable, a Low on these pins
enables their respective receivers. If not programmed as Auto Enable, these pins may be
used as general-purpose input signals.
DTRA, DTRB. Data Terminal Ready (outputs, active Low). These signals are modem con-
trol signals for the serial channels. They follow the state programmed into their respective
serial channels, and are multiplexed with Port C, bits 5 and 2, respectively.
IEI. Interrupt Enable In (input, active High). This signal is used with Interrupt Enable Out
(IEO) to form a priority daisy chain when there is more than one interrupt-driven device.
A High on this line indicates that no higher-priority device is requesting an interrupt.
IEO. Interrupt Enable Out (output, active High). This signal is used with Interrupt Enable
In (IEI) to form a priority daisy chain when there is more than one interrupt-driven device.
A High on this line indicates that this device is requesting an interrupt, and that no higher-
priority device, is not requesting an interrupt. A Low blocks any lower-priority devices
from requesting an interrupt.
IORQ. Input/Output Request (input, active Low). IORQ is used with RD, A0–A3, and CS
to transfer data between the KIO and the CPU. When IORQ, RD, and CS are active Low,
the device selected by A0–A3 transfers data to the CPU. When IORQ and CS are active
Low, but RD is active High, the device selected by A0–A3 is written into by the CPU.
When IORQ and M1 are both active Low, the KIO may respond with an interrupt vector
from its highest-priority interrupting device.
M1. Machine Cycle 1 (input, active Low). When M1 and RD are Low, the Z80 CPU
fetches an instruction from memory; the KIO decodes this cycle to determine if the RETI
instruction sequence is being executed. When M1 and IORQ are both active, the KIO
decodes the cycle to be an interrupt acknowledge, and may respond with a vector from its
highest-priority interrupting device.
PS011804-0612
Pin Descriptions