Z84C90_12 Datasheet, PDF (11/56 Pages) Zilog, Inc. – KIO Serial/Parallel Counter/Timer

Z84C90 KIO Serial/Parallel Counter/Timer
Product Specification
4
Parallel Interface Adapter (PIA) Logic Unit. This logic also offers an additional 8 bits of
I/O to the user, referred to as the PIA port (see Figure 3). This port, designated as Port C,
is bit-programmable for data transfers; each bit can be individually programmed as either
an input or an output. Bit direction control is performed through the programming of the
PIA Control Register. When programmed as outputs, the output data latches are pro-
grammed with an I/O write cycle; their state can be read with an I/O read cycle. When pro-
grammed as inputs, the state of the external pin is read with the I/O read cycle. This port
does not have handshake capabilities and offers no interrupt capabilities. This port is mul-
tiplexed to provide the additional modem and CPU control signals for the serial I/O logic
unit, when appropriate.
Data Bus
Port C
PC0–PC7
Dir.
Ctrl.
Figure 3. Parallel Interface Adapter Block Diagram
When a read from the PIA port occurs, input data will be latched when IORQ, CS and RD
all detected as active. The data bus will display this data as a result of the rising edge of the
clock input after this occurrence. When a write to the PIA port occurs, data will be written
as a result of the rising edge of the clock input after IORQ and CS have been detected as
active and RD has been detected as inactive.
Counter/Timer Logic (CTC) Unit. This logic unit provides the user with four individual
8-bit counter/timer channels that are compatible with the Z84C30 CTC (see Figure 4). The
counter/timers can be programmed by the CPU for a broad range of counting and timing
applications. Typical applications include event counting, interrupt and interval timing
and serial baud rate clock generation.
Each of the counter/timer channels, designated Channels 0 through 3, have an 8-bit pres-
caler (when used in timer mode) as well as its own 8-bit counter to provide a wide range of
count resolution. Each of the channels also have their own clock/trigger input to quantify
the counting process and an output to indicate zero crossing/time-out conditions. With
only one interrupt vector programmed into this logic unit, each channel can generate a
unique interrupt vector in response to the interrupt acknowledge cycle.
PS011804-0612
Block Descriptions