Z84C90_12 Datasheet, PDF (13/56 Pages) Zilog, Inc. – KIO Serial/Parallel Counter/Timer

Z84C90 KIO Serial/Parallel Counter/Timer
Product Specification
6
Channel A
Control
and
Status
Registers
Channel A
Serial
Data
Channel
Clocks
Sync
Wait/Ready
Internal
Control
Logic
Data
8
Control
7
CPU
Bus
I/O
Interrupt
Control
Lines
Interrupt
Control
Logic
Channel A
Control
and
Status
I
n
t
e
r
Channel B
n
Control
a
and
l
Status
B
u
s
Channel B
Modem or
Other
Control
Modem or
Other
Control
Serial
Data
Channel
Clocks
Sync
Wait/Ready
Channel B
Control
and
Status
Registers
Figure 5. SIO Block Diagram
In the default state of the KIO, each serial channel supports full duplex communication
with separate transmit and receive data lines, two modem control signals (CTS and DCD)
and separate transmit and receive clock inputs. Optionally, additional modem and CPU/
DMA control signals can be obtained through the PIA port.
For more information about the operation of this portion of the logic, please refer to the
Z8420/Z84C20 PIO Product Specification (PS0180).
PS011804-0612
Block Descriptions