Z84C90_12 Datasheet, PDF (25/56 Pages) Zilog, Inc. – KIO Serial/Parallel Counter/Timer

Z84C90 KIO Serial/Parallel Counter/Timer
Product Specification
18
Word must be set. When bit D4 of the Interrupt Control Word is set, the next word loaded
into the command register must be the Mask Control Word. To mask an input bit, the cor-
responding Mask Control Word bit must be a 1. See Figure 14.
D7 D6 D5 D4 D3 D2 D1 D0
MB0-MB7 Mask Bits
A bit is monitored for an interrupt
if it is defined as an input and the
mask bit is set to 0.
Figure 14. PIO Mask Control Word
Interrupt Disable Word. When bits B3 to B0 are loaded with 0011, the command register
functions as the Interrupt Disable Word Register. This word can be used to enable or dis-
able a port’s interrupts without change the remainder of the port’s interrupt conditions.
See Figure 15.
D7 D6 D5 D4 0 0 1 1
Identifies interrupt disable word
1 = Don’t care
0 = Interrupt disable
1 = Interrupt enable
Figure 15. PIO Interrupt Disable Word
CTC Registers
The CTC registers apply to channels 0, 1, 2 and 3 (additionally, see the Register Address
Decoding for the KIO section on page 13). For more information about these CTC regis-
ters, please consult the Z80 CPU Peripherals User Manual (UM0081).
Channel Control Word. This word sets the operating modes and parameters as described
in the following paragraphs. Bit D0 of the CTC Register must be a 1 to indicate a Control
Word; otherwise, it is an Interrupt Vector Word. See Figure 16.
PS011804-0612
Register Programming