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Z84C90_12 Datasheet, PDF (48/56 Pages) Zilog, Inc. – KIO Serial/Parallel Counter/Timer
Z84C90 KIO Serial/Parallel Counter/Timer
Product Specification
41
Table 5. AC Characteristics of the Z84C90 (Continued)
8 MHz
10MHz1,6 12.5MHz1,6
No. Symbol
Parameter
Min Max Min Max Min Max U/M
SIO Timing (continued)
50 TwPh
Pulse Width High
150
120
100
ns
51 TwPI
Pulse Width Low
150
120
100
ns
52 TcTxC
TxC Cycle Time
250 DC 200 DC 160 DC ns
53 TwTxCh
TxC Width High
85 DC 80 DC 70 DC ns
54 TwTxCl
TxC Width Low
85 DC 80 DC 70 DC ns
55 TrTxC
TxC Rise Time
60
60
60 ns
56 TfTxC
TxC Fall Time
60
60
60 ns
57 TdTxCf(TxD) TxC Fall to TxD Delay (x1 mode)
160
120
115 ns
58 TdTxCf(W/Rf) TxC Fall to WT/RDY Fall Delay  5
9
5
9
(Ready Mode)5
59 TdTxCf(INTf) TxC Fall to INT Fall Delay5
5
9
5
9
59 ns
59 ns
60 TcRxC
RxC Cycle Time
250 DC 200 DC 160 DC ns
61 TwRxCh
RxC Width High
85 DC 80 DC 70 DC ns
62 TwRxCl
RxC Width Low
85 DC 80 DC 70 DC ns
63 TrRxC
RxC Rise Time
60
60
60 ns
64 TfRxC
RxC Fall Time
60
60
60 ns
65 TsRxD(RxCr) RxD to RxC Rise Setup
0
0
0
ns
66 ThRxCr(RxD) RxC Rise to RxD Hold Time
80
60
50
ns
67 TdRxCr(W/Rf) RxC Rise to W/RDY Fall Delay
(Ready Mode)5
68 TdRxCf(INTf) RxC to INT Fall Delay5
10 13 10 13 10 13 ns
10 13 10 13 10 13 ns
69 TdRxCr
(SYNCf)
RxC Rise to SYNC Fall Delay
(Output Mode)
4
7
4
7
4
7 ns
Notes:
1. Maximum SIO data rate is fCLOCK ÷ by 5, in which fCLOCK = 1 ÷ TCC.
2. For a Z80 CPU operating above 8MHz, one wait state is required to meet this parameter.
3. These daisy chain parameters include contributions from the PIO, SIO and CTC cells, and vary slightly
depending on how they are ordered by the KIO Command Register.
4. Counter mode only; when using a cycle time less than 3 TcC, parameter #37 must be met.
5. Units are TcC.
6. If the CPU is a Z80 CPU and if it is required to have multiple Z80 peripherals in the system, then the time period
between M1 to IORQ must be extended.
7. Any open-drain output must add a Register-Capacitor (RC) time constant to the specification value.
PS011804-0612
AC Characteristics