XC4013E-3PQ160I Datasheet, PDF (9/68 Pages) Xilinx, Inc – XC4000E and XC4000X Series Field Programmable Gate Arrays

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XC4000E and XC4000X Series Field Programmable Gate Arrays
tions of the CLB, with the exception of the redefinition of the
control signals. In 16x2 and 16x1 modes, the H’ function
generator can be used to implement Boolean functions of
F’, G’, and D1, and the D flip-flops can latch the F’, G’, H’, or
D0 signals.
Single-Port Edge-Triggered Mode
Edge-triggered (synchronous) RAM simplifies timing
requirements. XC4000 Series edge-triggered RAM timing
operates like writing to a data register. Data and address
are presented. The register is enabled for writing by a logic
High on the write enable input, WE. Then a rising or falling
clock edge loads the data into the register, as shown in
Figure 3.
WCLK (K)
T_WPS
nals. An internal write pulse is generated that performs the
write. See Figure 4 and Figure 5 for block diagrams of a
CLB configured as 16x2 and 32x1 edge-triggered, sin-
gle-port RAM.
The relationships between CLB pins and RAM inputs and
outputs for single-port, edge-triggered mode are shown in
Table 5.
The Write Clock input (WCLK) can be configured as active
on either the rising edge (default) or the falling edge. It uses
the same CLB pin (K) used to clock the CLB flip-flops, but it
can be independently inverted. Consequently, the RAM
output can optionally be registered within the same CLB
either by the same clock edge as the RAM, or by the oppo-
site edge of this clock. The sense of WCLK applies to both
function generators in the CLB when both are configured
as RAM.
WE
DATA IN
T_WSS
T_WHS
T_DSS
T_DHS
T_ASS
T_AHS
The WE pin is active-High and is not invertible within the
CLB.
Note: The pulse following the active edge of WCLK (T_WPS
in Figure 3) must be less than one millisecond wide. For
most applications, this requirement is not overly restrictive;
however, it must not be forgotten. Stopping WCLK at this
6
point in the write cycle could result in excessive current and
even damage to the larger devices if many CLBs are con-
ADDRESS
figured as edge-triggered RAM.
Table 5: Single-Port Edge-Triggered RAM Signals
T_ILO
T_WOS
T_ILO
RAM Signal
CLB Pin
D
D0 or D1 (16x2,
Function
Data In
DATA OUT
OLD
NEW
16x1), D0 (32x1)
X6461
Figure 3: Edge-Triggered RAM Write Timing
A[3:0]
A[4]
WE
F1-F4 or G1-G4
D1 (32x1)
WE
Address
Address
Write Enable
Complex timing relationships between address, data, and
write enable signals are not required, and the external write
enable pulse becomes a simple clock enable. The active
edge of WCLK latches the address, input data, and WE sig-
WCLK
SPO
(Data Out)
K
F’ or G’
Clock
Single Port Out
(Data Out)
May 14, 1999 (Version 1.6)
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