XC4013E-3PQ160I Datasheet, PDF (37/68 Pages) Xilinx, Inc – XC4000E and XC4000X Series Field Programmable Gate Arrays

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XC4000E and XC4000X Series Field Programmable Gate Arrays
Table 16: Pin Descriptions (Continued)
I/O
I/O
During After
Pin Name Config. Config.
Pin Description
If boundary scan is used, these pins are Test Data In, Test Clock, and Test Mode Select
inputs respectively. They come directly from the pads, bypassing the IOBs. These pins
TDI, TCK,
TMS
I
I/O
or I
(JTAG)
can also be used as inputs to the CLB logic after configuration is completed.
If the BSCAN symbol is not placed in the design, all boundary scan functions are inhib-
ited once configuration is completed, and these pins become user-programmable I/O.
The pins can be used automatically or user-constrained. To use them, use "LOC=" or
place the library components TDI, TCK, and TMS instead of the usual pad symbols. In-
put or output buffers must still be used.
High During Configuration (HDC) is driven High until the I/O go active. It is available as
HDC
O
I/O a control output indicating that configuration is not yet completed. After configuration,
HDC is a user-programmable I/O pin.
Low During Configuration (LDC) is driven Low until the I/O go active. It is available as a
LDC
O
I/O control output indicating that configuration is not yet completed. After configuration,
LDC is a user-programmable I/O pin.
Before and during configuration, INIT is a bidirectional signal. A 1 kΩ - 10 kΩ external
pull-up resistor is recommended.
As an active-Low open-drain output, INIT is held Low during the power stabilization and
INIT
I/O
I/O
internal clearing of the configuration memory. As an active-Low input, it can be used
to hold the FPGA in the internal WAIT state before the start of configuration. Master
6
mode devices stay in a WAIT state an additional 30 to 300 µs after INIT has gone High.
During configuration, a Low on this output indicates that a configuration data error has
occurred. After the I/O go active, INIT is a user-programmable I/O pin.
Four Primary Global inputs each drive a dedicated internal global net with short delay
PGCK1 -
and minimal skew. If not used to drive a global buffer, any of these pins is a user-pro-
PGCK4
(XC4000E
Weak
Pull-up
I or I/O
grammable I/O.
The PGCK1-PGCK4 pins drive the four Primary Global Buffers. Any input pad symbol
only)
connected directly to the input of a BUFGP symbol is automatically placed on one of
these pins.
Four Secondary Global inputs each drive a dedicated internal global net with short delay
SGCK1 -
and minimal skew. These internal global nets can also be driven from internal logic. If
SGCK4
(XC4000E
Weak
Pull-up
I or I/O
not used to drive a global net, any of these pins is a user-programmable I/O pin.
The SGCK1-SGCK4 pins provide the shortest path to the four Secondary Global Buff-
only)
ers. Any input pad symbol connected directly to the input of a BUFGS symbol is auto-
matically placed on one of these pins.
Eight inputs can each drive a Global Low-Skew buffer. In addition, each can drive a Glo-
GCK1 -
bal Early buffer. Each pair of global buffers can also be driven from internal logic, but
GCK8
(XC4000X
Weak
Pull-up
I or I/O
must share an input signal. If not used to drive a global buffer, any of these pins is a
user-programmable I/O.
only)
Any input pad symbol connected directly to the input of a BUFGLS or BUFGE symbol
is automatically placed on one of these pins.
FCLK1 -
Four inputs can each drive a Fast Clock (FCLK) buffer which can deliver a clock signal
FCLK4
to any IOB clock input in the octant of the die served by the Fast Clock buffer. Two Fast
(XC4000XLA
and
Weak
Pull-up
I or I/O
Clock buffers serve the two IOB octants on the left side of the die and the other two Fast
Clock buffers serve the two IOB octants on the right side of the die. On each side of the
XC4000XV
die, one Fast Clock buffer serves the upper octant and the other serves the lower octant.
only)
If not used to drive a Fast Clock buffer, any of these pins is a user-programmable I/O.
May 14, 1999 (Version 1.6)
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