XC4013E-3PQ160I Datasheet, PDF (51/68 Pages) Xilinx, Inc – XC4000E and XC4000X Series Field Programmable Gate Arrays

Product Obsolete or Under Obsolescence
R
XC4000E and XC4000X Series Field Programmable Gate Arrays
Q3
STARTUP
Q2
*
*
*
Q1/Q4
DONE
IN
IOBs OPERATIONAL PER CONFIGURATION
1
0
0
1
1
0
GLOBAL SET/RESET OF
ALL CLB AND IOB FLIP-FLOP
GSR ENABLE
GSR INVERT
STARTUP.GSR
STARTUP.GTS
GTS INVERT
GTS ENABLE
CONTROLLED BY STARTUP SYMBOL
IN THE USER SCHEMATIC (SEE
LIBRARIES GUIDE)
GLOBAL 3-STATE OF ALL IOBs
QS
R
DONE
" FINISHED "
1
ENABLES BOUNDARY
0
SCAN, READBACK AND
CONTROLS THE OSCILLATOR
Q0
Q1
Q2
Q3
Q4
FULL
LENGTH COUNT
S
Q
D
Q
1
D
Q
0
D
Q
D
Q
6
M
K
K
K
*
K
K
CLEAR MEMORY
CCLK
0
STARTUP.CLK
1
USER NET
M
*
* ^{CONFIGURATION BIT OPTIONS SELECTED BY USER IN "MAKEBITS"}
Figure 48: Start-up Logic
X1528
Readback
The user can read back the content of configuration mem-
ory and the level of certain internal nodes without interfer-
ing with the normal operation of the device.
Readback not only reports the downloaded configuration
bits, but can also include the present state of the device,
represented by the content of all flip-flops and latches in
CLBs and IOBs, as well as the content of function genera-
tors used as RAMs.
Note that in XC4000 Series devices, configuration data is
not inverted with respect to configuration as it is in XC2000
and XC3000 families.
XC4000 Series Readback does not use any dedicated
pins, but uses four internal nets (RDBK.TRIG, RDBK.DATA,
RDBK.RIP and RDBK.CLK) that can be routed to any IOB.
To access the internal Readback signals, place the READ-
BACK library symbol and attach the appropriate pad sym-
bols, as shown in Figure 49.
After Readback has been initiated by a High level on
RDBK.TRIG after configuration, the RDBK.RIP (Read In
Progress) output goes High on the next rising edge of
RDBK.CLK. Subsequent rising edges of this clock shift out
Readback data on the RDBK.DATA net.
Readback data does not include the preamble, but starts
with five dummy bits (all High) followed by the Start bit
(Low) of the first frame. The first two data bits of the first
frame are always High.
Each frame ends with four error check bits. They are read
back as High. The last seven bits of the last frame are also
read back as High. An additional Start bit (Low) and an
11-bit Cyclic Redundancy Check (CRC) signature follow,
before RDBK.RIP returns Low.
May 14, 1999 (Version 1.6)
6-55