XC4013E-3PQ160I Datasheet, PDF (41/68 Pages) Xilinx, Inc – XC4000E and XC4000X Series Field Programmable Gate Arrays

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XC4000E and XC4000X Series Field Programmable Gate Arrays
Table 17: Boundary Scan Instructions
Instruction I2
I1 I0
Test
Selected
TDO Source
I/O Data
Source
Optional
IBUF
To User
Logic
0 0 0 EXTEST
DR
DR
0 0 1 SAMPLE/PR DR
ELOAD
Pin/Logic
010
USER 1
BSCAN. User Logic
TDO1
011
USER 2
BSCAN. User Logic
TDO2
TDI
TMS
TCK
From
User Logic
BSCAN
TDI
TDO
TMS
DRCK
TCK
IDLE
TDO1
SEL1
TDO2
SEL2
TDO
To User
Logic
X2675
1 0 0 READBACK Readback Pin/Logic
Figure 43: Boundary Scan Schematic Example
Data
1 0 1 CONFIGURE DOUT
Disabled
Configuration
1 1 0 Reserved
—
—
1 1 1 BYPASS Bypass
—
Register
Configuration is the process of loading design-specific pro-
gramming data into one or more FPGAs to define the func-
tional operation of the internal blocks and their
interconnections. This is somewhat like loading the com-
mand registers of a programmable peripheral chip. XC4000
Bit 0 ( TDO end)
Bit 1
Bit 2
TDO.T
TDO.O
Top-edge IOBs (Right to Left)
Series devices use several hundred bits of configuration
data per CLB and its associated interconnects. Each con-
figuration bit defines the state of a static memory cell that
Left-edge IOBs (Top to Bottom)
controls either a function look-up table bit, a multiplexer
input, or an interconnect pass transistor. The XACTstep
6
MD1.T
MD1.O
MD1.I
MD0.I
MD2.I
Bottom-edge IOBs (Left to Right)
development system translates the design into a netlist file.
It automatically partitions, places and routes the logic and
generates the configuration data in PROM format.
Special Purpose Pins
Three configuration mode pins (M2, M1, M0) are sampled
Right-edge IOBs (Bottom to Top)
prior to configuration to determine the configuration mode.
(TDI end)
B SCANT.UPD
After configuration, these pins can be used as auxiliary
connections. M2 and M0 can be used as inputs, and M1
X6075
can be used as an output. The XACTstep development sys-
Figure 42: Boundary Scan Bit Sequence
tem does not use these resources unless they are explicitly
specified in the design entry. This is done by placing a spe-
Avoiding Inadvertent Boundary Scan
If TMS or TCK is used as user I/O, care must be taken to
ensure that at least one of these pins is held constant dur-
ing configuration. In some applications, a situation may
occur where TMS or TCK is driven during configuration.
This may cause the device to go into boundary scan mode
and disrupt the configuration process.
To prevent activation of boundary scan during configura-
tion, do either of the following:
cial pad symbol called MD2, MD1, or MD0 instead of the
input or output pad symbol.
In XC4000 Series devices, the mode pins have weak
pull-up resistors during configuration. With all three mode
pins High, Slave Serial mode is selected, which is the most
popular configuration mode. Therefore, for the most com-
mon configuration mode, the mode pins can be left uncon-
nected. (Note, however, that the internal pull-up resistor
value can be as high as 100 kΩ.) After configuration, these
pins can individually have weak pull-up or pull-down resis-
• TMS: Tie High to put the Test Access Port controller
in a benign RESET state
tors, as specified in the design. A pull-down resistor value
of 4.7 kΩ is recommended.
• TCK: Tie High or Low—don't toggle this clock input.
These pins are located in the lower left chip corner and are
For more information regarding boundary scan, refer to the
Xilinx Application Note XAPP 017.001, “Boundary Scan in
XC4000E Devices.“
near the readback nets. This location allows convenient
routing if compatibility with the XC2000 and XC3000 family
conventions of M0/RT, M1/RD is desired.
May 14, 1999 (Version 1.6)
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