XC4013E-3PQ160I Datasheet, PDF (54/68 Pages) Xilinx, Inc – XC4000E and XC4000X Series Field Programmable Gate Arrays

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XC4000E and XC4000X Series Field Programmable Gate Arrays
Table 22: Pin Functions During Configuration
SLAVE
SERIAL
<1:1:1>
M2(HIGH) (I)
M1(HIGH) (I)
M0(HIGH) (I)
HDC (HIGH)
LDC (LOW)
INIT
DONE
PROGRAM (I)
CCLK (I)
DIN (I)
DOUT
TDI
TCK
TMS
TDO
MASTER
SERIAL
<0:0:0>
M2(LOW) (I)
M1(LOW) (I)
M0(LOW) (I)
HDC (HIGH)
LDC (LOW)
INIT
DONE
PROGRAM (I)
CCLK (O)
DIN (I)
DOUT
TDI
TCK
TMS
TDO
CONFIGURATION MODE <M2:M1:M0>
SYNCH.
PERIPHERAL
<0:1:1>
ASYNCH.
MASTER
PERIPHERAL PARALLEL DOWN
<1:0:1>
<1:1:0>
M2(LOW) (I)
M2(HIGH) (I)
M2(HIGH) (I)
M1(HIGH) (I)
M1(LOW) (I)
M1(HIGH) (I)
M0(HIGH) (I) M0(HIGH) (I)
M0(LOW) (I)
HDC (HIGH)
HDC (HIGH)
HDC (HIGH)
LDC (LOW)
LDC (LOW)
LDC (LOW)
INIT
INIT
INIT
DONE
DONE
DONE
PROGRAM (I) PROGRAM (I) PROGRAM (I)
CCLK (I)
CCLK (O)
CCLK (O)
RDY/BUSY (O) RDY/BUSY (O)
RCLK (O)
RS (I)
CS0 (I)
DATA 7 (I)
DATA 7 (I)
DATA 7 (I)
DATA 6 (I)
DATA 6 (I)
DATA 6 (I)
DATA 5 (I)
DATA 5 (I)
DATA 5 (I)
DATA 4 (I)
DATA 4 (I)
DATA 4 (I)
DATA 3 (I)
DATA 3 (I)
DATA 3 (I)
DATA 2 (I)
DATA 2 (I)
DATA 2 (I)
DATA 1 (I)
DATA 1 (I)
DATA 1 (I)
DATA 0 (I)
DATA 0 (I)
DATA 0 (I)
DOUT
DOUT
DOUT
TDI
TDI
TDI
TCK
TCK
TCK
TMS
TMS
TMS
TDO
TDO
TDO
WS (I)
A0
A1
CS1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18*
A19*
A20*
A21*
MASTER
PARALLEL UP
<1:0:0>
M2(HIGH) (I)
M1(LOW) (I)
M0(LOW) (I)
HDC (HIGH)
LDC (LOW)
INIT
DONE
PROGRAM (I)
CCLK (O)
RCLK (O)
DATA 7 (I)
DATA 6 (I)
DATA 5 (I)
DATA 4 (I)
DATA 3 (I)
DATA 2 (I)
DATA 1 (I)
DATA 0 (I)
DOUT
TDI
TCK
TMS
TDO
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18*
A19*
A20*
A21*
USER
OPERATION
(I)
(O)
(I)
I/O
I/O
I/O
DONE
PROGRAM
CCLK (I)
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
SGCK4-GCK6-I/O
TDI-I/O
TCK-I/O
TMS-I/O
TDO-(O)
I/O
PGCK4-GCK7-I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
SGCK1-GCK8-I/O
PGCK1-GCK1-I/O
I/O
I/O
I/O
I/O
I/O
ALL OTHERS
6-58
May 14, 1999 (Version 1.6)