XC4013E-3PQ160I Datasheet, PDF (11/68 Pages) Xilinx, Inc – XC4000E and XC4000X Series Field Programmable Gate Arrays

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XC4000E and XC4000X Series Field Programmable Gate Arrays
Dual-Port Edge-Triggered Mode
Table 6: Dual-Port Edge-Triggered RAM Signals
In dual-port mode, both the F and G function generators
are used to create a single 16x1 RAM array with one write
port and two read ports. The resulting RAM array can be
read and written simultaneously at two independent
addresses. Simultaneous read and write operations at the
same address are also supported.
Dual-port mode always has edge-triggered write timing, as
shown in Figure 3.
Figure 6 shows a simple model of an XC4000 Series CLB
RAM Signal CLB Pin
D
D0
A[3:0]
F1-F4
DPRA[3:0]
WE
WCLK
SPO
G1-G4
WE
K
F’
DPO
G’
Function
Data In
Read Address for F,
Write Address for F and G
Read Address for G
Write Enable
Clock
Single Port Out
(addressed by A[3:0])
Dual Port Out
configured as dual-port RAM. One address port, labeled
(addressed by DPRA[3:0])
A[3:0], supplies both the read and write address for the F
function generator. This function generator behaves the
same as a 16x1 single-port edge-triggered RAM array. The
RAM output, Single Port Out (SPO), appears at the F func-
tion generator output. SPO, therefore, reflects the data at
address A[3:0].
The other address port, labeled DPRA[3:0] for Dual Port
Read Address, supplies the read address for the G function
Note: The pulse following the active edge of WCLK (T_WPS
in Figure 3) must be less than one millisecond wide. For
most applications, this requirement is not overly restrictive;
however, it must not be forgotten. Stopping WCLK at this
point in the write cycle could result in excessive current and
even damage to the larger devices if many CLBs are con-
figured as edge-triggered RAM.
generator. The write address for the G function generator, ^{Single-Port Level-Sensitive Timing Mode}
however, comes from the address A[3:0]. The output from _{Note: Edge-triggered mode is recommended for all new}
this 16x1 RAM array, Dual Port Out (DPO), appears at the
G function generator output. DPO, therefore, reflects the
designs. Level-sensitive mode, also called asynchronous
mode, is still supported for XC4000 Series backward-com-
6
data at address DPRA[3:0].
patibility with the XC4000 family.
Therefore, by using A[3:0] for the write address and
DPRA[3:0] for the read address, and reading only the DPO
output, a FIFO that can read and write simultaneously is
easily generated. Simultaneous access doubles the effec-
tive throughput of the FIFO.
Level-sensitive RAM timing is simple in concept but can be
complicated in execution. Data and address signals are
presented, then a positive pulse on the write enable pin
(WE) performs a write into the RAM at the designated
address. As indicated by the “level-sensitive” label, this
The relationships between CLB pins and RAM inputs and
outputs for dual-port, edge-triggered mode are shown in
Table 6. See Figure 7 on page 16 for a block diagram of a
CLB configured in this mode.
WE
D
DPRA[3:0]
A[3:0]
RAM16X1D Primitive
WE
D
AR[3:0]
AW[3:0]
G Function Generator
WE
D
AR[3:0]
AW[3:0]
D
Q
DPO (Dual Port Out)
Registered DPO
D
Q
SPO (Single Port Out)
Registered SPO
RAM acts like a latch. During the WE High pulse, changing
the data lines results in new data written to the old address.
Changing the address lines while WE is High results in spu-
rious data written to the new address—and possibly at
other addresses as well, as the address lines inevitably do
not all change simultaneously.
The user must generate a carefully timed WE signal. The
delay on the WE signal and the address lines must be care-
fully verified to ensure that WE does not become active
until after the address lines have settled, and that WE goes
inactive before the address lines change again. The data
must be stable before and after the falling edge of WE.
In practical terms, WE is usually generated by a 2X clock. If
a 2X clock is not available, the falling edge of the system
clock can be used. However, there are inherent risks in this
approach, since the WE pulse must be guaranteed inactive
WCLK
F Function Generator
before the next rising edge of the system clock. Several
older application notes are available from Xilinx that dis-
cuss the design of level-sensitive RAMs.
X6755
Figure 6: XC4000 Series Dual-Port RAM, Simple
Model
However, the edge-triggered RAM available in the XC4000
Series is superior to level-sensitive RAM for almost every
application.
May 14, 1999 (Version 1.6)
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