XC4013E-3PQ160I Datasheet, PDF (47/68 Pages) Xilinx, Inc – XC4000E and XC4000X Series Field Programmable Gate Arrays

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XC4000E and XC4000X Series Field Programmable Gate Arrays
Low. During this time delay, or as long as the PROGRAM rise time is excessive or poorly defined. As long as PRO-
input is asserted, the configuration logic is held in a Config- GRAM is Low, the FPGA keeps clearing its configuration
uration Memory Clear state. The configuration-memory memory. When PROGRAM goes High, the configuration
frames are consecutively initialized, using the internal oscil- memory is cleared one more time, followed by the begin-
lator.
ning of configuration, provided the INIT input is not exter-
At the end of each complete pass through the frame
addressing, the power-on time-out delay circuitry and the
level of the PROGRAM pin are tested. If neither is asserted,
nally held Low. Note that a Low on the PROGRAM input
automatically forces a Low on the INIT output. The XC4000
Series PROGRAM pin has a permanent weak pull-up.
the logic initiates one additional clearing of the configura- Using an open-collector or open-drain driver to hold INIT
tion frames and then tests the INIT input.
Low before the beginning of configuration causes the
Initialization
FPGA to wait after completing the configuration memory
clear operation. When INIT is no longer held Low exter-
During initialization and configuration, user pins HDC, LDC, ^{nally, the device determines its configuration mode by cap-}
INIT and DONE provide status outputs for the system inter- ^{turing its mode pins, and is ready to start the configuration}
face. The outputs LDC, INIT and DONE are held Low and ^{process. A master device waits up to an additional 250 µs}
HDC is held High starting at the initial application of power. ^{to make sure that any slaves in the optional daisy chain}
The open drain INIT pin is released after the final initializa- ^{have seen that INIT is High.}
tion pass through the frame addresses. There is a deliber- _Start-Up
ate delay of 50 to 250 µs (up to 10% longer for low-voltage
devices) before a Master-mode device recognizes an inac- ^{Start-up is the transition from the configuration process to}
tive INIT. Two internal clocks after the INIT pin is recognized ^{the intended user operation. This transition involves a}
as High, the FPGA samples the three mode lines to deter- ^{change from one clock source to another, and a change}
mine the configuration mode. The appropriate interface
lines become active and the configuration preamble and
from interfacing parallel or serial configuration data where
most outputs are 3-stated, to normal operation with I/O pins
6
data can be loaded.Configuration
active in the user-system. Start-up must make sure that the
user-logic ‘wakes up’ gracefully, that the outputs become
The 0010 preamble code indicates that the following 24 bits _{active without causing contention with the configuration sig-}
represent the length count. The length count is the total _{nals, and that the internal flip-flops are released from the}
number of configuration clocks needed to load the com- _{global Reset or Set at the right time.}
plete configuration data. (Four additional configuration
clocks are required to complete the configuration process,
as discussed below.) After the preamble and the length
count have been passed through to all devices in the daisy
Figure 47 describes start-up timing for the three Xilinx fam-
ilies in detail. The configuration modes can use any of the
four timing sequences.
chain, DOUT is held High to prevent frame start bits from To access the internal start-up signals, place the STARTUP
reaching any daisy-chained devices.
library symbol.
A specific configuration bit, early in the first frame of a mas-
ter device, controls the configuration-clock rate and can
increase it by a factor of eight. Therefore, if a fast configu-
ration clock is selected by the bitstream, the slower clock
rate is used until this configuration bit is detected.
Each frame has a start field followed by the frame-configu-
ration data bits and a frame error field. If a frame data error
is detected, the FPGA halts loading, and signals the error
by pulling the open-drain INIT pin Low. After all configura-
tion frames have been loaded into an FPGA, DOUT again
follows the input data so that the remaining data is passed
on to the next device.
Delaying Configuration After Power-Up
There are two methods of delaying configuration after
power-up: put a logic Low on the PROGRAM input, or pull
the bidirectional INIT pin Low, using an open-collector
(open-drain) driver. (See Figure 46 on page 50.)
A Low on the PROGRAM input is the more radical
approach, and is recommended when the power-supply
Start-up Timing
Different FPGA families have different start-up sequences.
The XC2000 family goes through a fixed sequence. DONE
goes High and the internal global Reset is de-activated one
CCLK period after the I/O become active.
The XC3000A family offers some flexibility. DONE can be
programmed to go High one CCLK period before or after
the I/O become active. Independent of DONE, the internal
global Reset is de-activated one CCLK period before or
after the I/O become active.
The XC4000 Series offers additional flexibility. The three
events — DONE going High, the internal Set/Reset being
de-activated, and the user I/O going active — can all occur
in any arbitrary sequence. Each of them can occur one
CCLK period before or after, or simultaneous with, any of
the others. This relative timing is selected by means of soft-
ware options in the bitstream generation software.
May 14, 1999 (Version 1.6)
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