XC4013E-3PQ160I Datasheet, PDF (12/68 Pages) Xilinx, Inc – XC4000E and XC4000X Series Field Programmable Gate Arrays

Product Obsolete or Under Obsolescence
R
XC4000E and XC4000X Series Field Programmable Gate Arrays
4
C1 • • • C4
WE
D1
D0
EC
G1 • • • G4
4
D_IN
WRITE
16-LATCH
DECODER
ARRAY
MUX
G'
4
1 of 16
LATCH
ENABLE
WRITE PULSE
READ
ADDRESS
D_IN
F1 • • • F4
4
K
(CLOCK)
4
LATCH
ENABLE
WRITE
DECODER
1 of 16
16-LATCH
ARRAY
MUX
WRITE PULSE
READ
ADDRESS
Figure 7: 16x1 Edge-Triggered Dual-Port RAM
F'
X6748
Figure 8 shows the write timing for level-sensitive, sin-
gle-port RAM.
The relationships between CLB pins and RAM inputs and
outputs for single-port level-sensitive mode are shown in
Table 7.
Figure 9 and Figure 10 show block diagrams of a CLB con-
figured as 16x2 and 32x1 level-sensitive, single-port RAM.
Initializing RAM at Configuration
Both RAM and ROM implementations of the XC4000
Series devices are initialized during configuration. The ini-
tial contents are defined via an INIT attribute or property
attached to the RAM or ROM symbol, as described in the
schematic library guide. If not defined, all RAM contents
are initialized to all zeros, by default.
RAM initialization occurs only during configuration. The
RAM content is not affected by Global Set/Reset.
Table 7: Single-Port Level-Sensitive RAM Signals
RAM Signal
D
A[3:0]
WE
O
CLB Pin
D0 or D1
F1-F4 or G1-G4
WE
F’ or G’
Function
Data In
Address
Write Enable
Data Out
ADDRESS
TWC
TAS
WRITE ENABLE
DATA IN
Figure 8: Level-Sensitive RAM Write Timing
TWP
TDS
REQUIRED
TAH
TDH
X6462
6-16
May 14, 1999 (Version 1.6)