XC4013E-3PQ160I Datasheet, PDF (21/68 Pages) Xilinx, Inc – XC4000E and XC4000X Series Field Programmable Gate Arrays

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XC4000E and XC4000X Series Field Programmable Gate Arrays
Output Multiplexer/2-Input Function Generator
Other IOB Options
(XC4000X only)
There are a number of other programmable options in the
As shown in Figure 16 on page 21, the output path in the _{XC4000 Series IOB.}
XC4000X IOB contains an additional multiplexer not avail-
able in the XC4000E IOB. The multiplexer can also be con-
Pull-up and Pull-down Resistors
figured as a 2-input function generator, implementing a
pass-gate, AND-gate, OR-gate, or XOR-gate, with 0, 1, or 2
inverted inputs. The logic used to implement these func-
tions is shown in the upper gray area of Figure 16.
Programmable pull-up and pull-down resistors are useful
for tying unused pins to Vcc or Ground to minimize power
consumption and reduce noise sensitivity. The configurable
pull-up resistor is a p-channel transistor that pulls to Vcc.
When configured as a multiplexer, this feature allows two
output signals to time-share the same output pad; effec-
The configurable pull-down resistor is an n-channel transis-
tor that pulls to Ground.
tively doubling the number of device outputs without requir-
ing a larger, more expensive package.
The value of these resistors is 50 kΩ − 100 kΩ. This high
value makes them unsuitable as wired-AND pull-up resis-
When the MUX is configured as a 2-input function genera- ^tors.
tor, logic can be implemented within the IOB itself. Com- _{The pull-up resistors for most user-programmable IOBs are}
bined with a Global Early buffer, this arrangement allows _{active during the configuration process. See Table 22 on}
very high-speed gating of a single signal. For example, a _{page 58 for a list of pins with pull-ups active before and dur-}
wide decoder can be implemented in CLBs, and its output _{ing configuration.}
gated with a Read or Write Strobe Driven by a BUFGE
buffer, as shown in Figure 19. The critical-path pin-to-pin
delay of this circuit is less than 6 nanoseconds.
After configuration, voltage levels of unused pads, bonded
or un-bonded, must be valid logic levels, to reduce noise
sensitivity and avoid excess current. Therefore, by default,
As shown in Figure 16, the IOB input pins Out, Output
Clock, and Clock Enable have different delays and different
unused pads are configured with the internal pull-up resis-
tor active. Alternatively, they can be individually configured
6
flexibilities regarding polarity. Additionally, Output Clock _{with the pull-down resistor, or as a driven output, or to be}
sources are more limited than the other inputs. Therefore, _{driven by an external source. To activate the internal}
the Xilinx software does not move logic into the IOB func- _{pull-up, attach the PULLUP library component to the net}
tion generators unless explicitly directed to do so.
attached to the pad. To activate the internal pull-down,
The user can specify that the IOB function generator be
used, by placing special library symbols beginning with the
attach the PULLDOWN library component to the net
attached to the pad.
letter “O.” For example, a 2-input AND-gate in the IOB func-
tion generator is called OAND2. Use the symbol input pin
Independent Clocks
labelled “F” for the signal on the critical path. This signal is ^{Separate clock signals are provided for the input and output}
placed on the OK pin — the IOB input with the shortest ^{flip-flops. The clock can be independently inverted for each}
delay to the function generator. Two examples are shown in ^{flip-flop within the IOB, generating either falling-edge or ris-}
Figure 20.
ing-edge triggered flip-flops. The clock inputs for each IOB
are independent, except that in the XC4000X, the Fast
IPAD
Capture latch shares an IOB input with the output clock pin.
BUFGE
from
internal
logic
F
OAND2
OPAD
FAST
X9019
Figure 19: Fast Pin-to-Pin Path in XC4000X
OMUX2
F
D0
O
D1
Early Clock for IOBs (XC4000X only)
Special early clocks are available for IOBs. These clocks
are sourced by the same sources as the Global Low-Skew
buffers, but are separately buffered. They have fewer loads
and therefore less delay. The early clock can drive either
the IOB output clock or the IOB input clock, or both. The
early clock allows fast capture of input data, and fast
clock-to-output on output data. The Global Early buffers
that drive these clocks are described in “Global Nets and
Buffers (XC4000X only)” on page 37.
Global Set/Reset
OAND2
X6598
S0
X6599
Figure 20: AND & MUX Symbols in XC4000X IOB
As with the CLB registers, the Global Set/Reset signal
(GSR) can be used to set or clear the input and output reg-
isters, depending on the value of the INIT attribute or prop-
erty. The two flip-flops can be individually configured to set
May 14, 1999 (Version 1.6)
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