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| XC4013E-3PQ160I Datasheet, PDF (64/68 Pages) Xilinx, Inc – XC4000E and XC4000X Series Field Programmable Gate Arrays | |||
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Product Obsolete or Under Obsolescence
R
XC4000E and XC4000X Series Field Programmable Gate Arrays
Conï¬guration Switching Characteristics
Vcc
T POR
PROGRAM
INIT
T PI
CCLK OUTPUT or INPUT
TICCK
X1532
M0, M1, M2
(Required)
VALID
RE-PROGRAM
>300 ns
TCCLK
DONE RESPONSE
I/O
<300 ns
<300 ns
Master Modes (XC4000E/EX)
Description
Symbol
Min
Power-On Reset
Program Latency
M0 = High
TPOR
10
M0 = Low
TPOR
40
TPI
30
CCLK (output) Delay
CCLK (output) Period, slow
CCLK (output) Period, fast
TICCK
40
TCCLK
640
TCCLK
80
Master Modes (XC4000XL)
Description
Symbol
Min
Power-On Reset
Program Latency
M0 = High
TPOR
10
M0 = Low
TPOR
40
TPI
30
CCLK (output) Delay
CCLK (output) Period, slow
CCLK (output) Period, fast
Slave and Peripheral Modes (All)
Power-On Reset
Program Latency
Description
TICCK
40
TCCLK
540
TCCLK
67
Symbol
Min
TPOR
10
TPI
30
CCLK (input) Delay (required)
CCLK (input) Period (required)
TICCK
4
TCCLK
100
Max
40
130
200
250
2000
250
Units
ms
ms
µs per
CLB column
µs
ns
ns
Max
40
130
200
250
1600
200
Units
ms
ms
µs per
CLB column
µs
ns
ns
Max
Units
33
ms
200
µs per
CLB column
µs
ns
6-68
May 14, 1999 (Version 1.6)
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