XC4013E-3PQ160I Datasheet, PDF (33/68 Pages) Xilinx, Inc – XC4000E and XC4000X Series Field Programmable Gate Arrays

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XC4000E and XC4000X Series Field Programmable Gate Arrays
Global Nets and Buffers (XC4000X only)
Early and Global Low-Skew buffers share a common input;
Eight vertical longlines in each CLB column are driven by ^{they cannot be driven by two different signals.}
special global buffers. These longlines are in addition to the
vertical longlines used for standard interconnect. The glo-
bal lines are broken in the center of the array, to allow faster
distribution and to minimize skew across the whole array.
Each half-column global line has its own buffered multi-
plexer, as shown in Figure 35. The top and bottom global
lines cannot be connected across the center of the device,
as this connection might introduce unacceptable skew. The
top and bottom halves of the global lines must be sepa-
rately driven — although they can be driven by the same
global buffer.
The eight global lines in each CLB column can be driven by
either of two types of global buffers. They can also be
driven by internal logic, because they can be accessed by
Choosing an XC4000X Clock Buffer
The clocking structure of the XC4000X provides a large
variety of features. However, it can be simple to use, with-
out understanding all the details. The software automati-
cally handles clocks, along with all other routing, when the
appropriate clock buffer is placed in the design. In fact, if a
buffer symbol called BUFG is placed, rather than a specific
type of buffer, the software even chooses the buffer most
appropriate for the design. The detailed information in this
section is provided for those users who want a finer level of
control over their designs.
If fine control is desired, use the following summary and
Table 15 on page 35 to choose an appropriate clock buffer.
single, double, and quad lines at the top, bottom, half, and • The simplest thing to do is to use a Global Low-Skew
quarter points. Consequently, the number of different
buffer.
clocks that can be used simultaneously in an XC4000X • If a faster clock path is needed, try a BUFG. The
device is very large.
software will first try to use a Global Low-Skew Buffer. If
There are four global lines feeding the IOBs at the left edge
timing requirements are not met, a faster buffer will
of the device. IOBs along the right edge have eight global
automatically be used.
lines. There is a single global line along the top and bottom ^{• If a single quadrant of the chip is sufficient for the}
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edges with access to the IOBs. All IOB global lines are bro-
clocked logic, and the timing requires a faster clock than
ken at the center. They cannot be connected across the
the Global Low-Skew buffer, use a Global Early buffer.
center of the device, as this connection might introduce
unacceptable skew.
IOB global lines can be driven from two types of global buff-
ers, or from local interconnect. Alternatively, top and bottom
IOBs can be clocked from the global lines in the adjacent
CLB column.
Global Low-Skew Buffers
Each corner of the XC4000X device has two Global
Low-Skew buffers. Any of the eight Global Low-Skew buff-
ers can drive any of the eight vertical Global lines in a col-
umn of CLBs. In addition, any of the buffers can drive any of
the four vertical lines accessing the IOBs on the left edge of
Two different types of clock buffers are available in the ^{the device, and any of the eight vertical lines accessing the}
XC4000X:
IOBs on the right edge of the device. (See Figure 36 on
• Global Low-Skew Buffers (BUFGLS)
page 38.)
• Global Early Buffers (BUFGE)
IOBs at the top and bottom edges of the device are
Global Low-Skew Buffers are the standard clock buffers.
They should be used for most internal clocking, whenever a
large portion of the device must be driven.
accessed through the vertical Global lines in the CLB array,
as in the XC4000E. Any Global Low-Skew buffer can,
therefore, access every IOB and CLB in the device.
Global Early Buffers are designed to provide a faster clock
access, but CLB access is limited to one-fourth of the
The Global Low-Skew buffers can be driven by either
semi-dedicated pads or internal logic.
device. They also facilitate a faster I/O interface.
To use a Global Low-Skew buffer, instantiate a BUFGLS
Figure 35 is a conceptual diagram of the global net struc-
ture in the XC4000X.
element in a schematic or in HDL code. If desired, attach a
LOC attribute or property to direct placement to the desig-
nated location. For example, attach a LOC=T attribute or
Global Early buffers and Global Low-Skew buffers share a _{property to direct that a BUFGLS be placed in one of the}
single pad. Therefore, the same IPAD symbol can drive one _{two Global Low-Skew buffers on the top edge of the device,}
buffer of each type, in parallel. This configuration is particu- _{or a LOC=TR to indicate the Global Low-Skew buffer on the}
larly useful when using the Fast Capture latches, as _{top edge of the device, on the right.}
described in “IOB Input Signals” on page 20. Paired Global
May 14, 1999 (Version 1.6)
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