XC4013E-3PQ160I Datasheet, PDF (63/68 Pages) Xilinx, Inc – XC4000E and XC4000X Series Field Programmable Gate Arrays

R
WS/CS0
RS, CS1
D0-D7
CCLK
RDY/BUSY
DOUT
Product Obsolete or Under Obsolescence
XC4000E and XC4000X Series Field Programmable Gate Arrays
Write to LCA
Read Status
RS, CS0
1 _TCA
2 _TDC
3 _TCD
WS, CS1
7
4
READY
BUSY
D7
T_WTRB ⁴
6 _TBUSY
Previous Byte D6
D7
D0
D1
D2
X6097
Description
Symbol
Min
Effective Write time
1
T_CA
100
(CS0, WS=Low; RS, CS1=High)
Write _{DIN setup time}
2
T_DC
60
DIN hold time
3
T_CD
0
RDY/BUSY delay after end of
Write or Read
4
T_WTRB
Max
Units
ns
6
ns
ns
60
ns
RDY RDY/BUSY active after beginning
7
of Read
60
ns
RDY/BUSY Low output (Note 4)
6
T_BUSY
2
9
CCLK
periods
Notes:
1. Configuration must be delayed until the INIT pins of all daisy-chained FPGAs are High.
2. The time from the end of WS to CCLK cycle for the new byte of data depends on the completion of previous byte
processing and the phase of the internal timing generator for CCLK.
3. CCLK and DOUT timing is tested in slave mode.
4. T_BUSY indicates that the double-buffered parallel-to-serial converter is not yet ready to receive new data. The shortest
T_BUSY occurs when a byte is loaded into an empty parallel-to-serial converter. The longest T_BUSY occurs when a new word
is loaded into the input register before the second-level buffer has started shifting out data
This timing diagram shows very relaxed requirements. Data need not be held beyond the rising edge of WS. RDY/BUSY will
go active within 60 ns after the end of WS. A new write may be asserted immediately after RDY/BUSY goes Low, but write
may not be terminated until RDY/BUSY has been High for one CCLK period.
Figure 59: Asynchronous Peripheral Mode Programming Switching Characteristics
May 14, 1999 (Version 1.6)
6-67